-
Hi Alex,
Thanks for sharing your verilog-pcie library! I have been running simulations for the various components and examples as well as studying the source but still have a few questions. For all…
-
PR #41 highlighted the need for AXI snippets. @Bochlin provided a starting point for the requirements of such snippets. Their comment is reported below, and this issue is the place to discuss this top…
-
Hi
axi_cdc uses fifos that don't infer dual SRAM. Fifo is implemented using registers, and it is very slow.
In my design, I had to lower fifo depth to 8 words in order to be able to run at 100mhz.…
-
Thanks for the nice tutorial!! Would it be possible to add the `axi_gpio_switches_leds.overlay` that enables the AXI GPIO controller IP core(s) in the design?
-
* Use https://github.com/pulp-platform/axi/tree/axi_lite_dw_converter/src, wait until it is merged into main in `axi`
-
Here's the patch I've applied to litex (latest upstream version, incl. all dependencies). Also shown are the commands I'm using to (attempt to) pull data out of the SoC with `litescope_cli`:
```dif…
-
Instead of always returning [ok](https://github.com/esynr3z/corsair/blob/master/corsair/templates/axil2lb_verilog.j2#L77), if trying to write to a read only address, or read a write only, or have a ba…
-
### The problem
When laying out a proof tree, no line is displayed above axioms. However, I often want a line above those. Typically, I want one above axioms, but none above the prerequisites of a …
-
implement a wrapper to bring to nearest AXI burst size. Need to add a pad & crop to bring any pixel size up to burst size. Need to add infrastructure to pad/crop the input image & output image.
-
As discussed in https://github.com/llvm/circt/issues/2254 , `firtool -verilog` will append the contents of the `firrtl_black_box_resource_files.f` file into the output verilog file. This results in no…