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Hi Charles,
when performing **reading** operations during the **simulation** and **on FPGA**, `SCOPE_HART_DCACHE_WRITEBACK` counter value is increased, which was not expected.
#define SCOPE_H…
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Hey there!
Can we port ztachip to the following FPGAs with less than 100,000 LUTs:
1. Digilent Cmod A7-35T: Artix-7 with 35,000 LUTs
2. Cmod A7-15T: Artix-7 FPGA Module with 15,000 LUTs
3. CrossLi…
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To continue we started with the official website https://github.com/hex-five/multizone-sdk on our virtual box with ubuntu machine and we are trying to connect "Arty A7 100T" board. Now we are working …
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Hi everyone,
I have a dubs about the regeneration process of the Verilog of the VexRiscV core, in particular I trying to modify the core inside the pythondata-cpu-vexriscv_smp repository and adding…
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Hi !
I am working on the digilent Arty A7-100T board with LiteX version 2022.08. I am using the UARTBone for communication with LiteScope.
I want to observe the registers of the CVA6 RISC-V CPU…
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I have a NiteFury decvice. I do not have a JTAG cable. So do not want to land into a situation where NiteFury is `bricked'.
Is there any way to leave the factory design untouched or any way to reco…
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Hello, i am trying to program a zedboard using openocd to a ibex core. The output error is this one:
```
./util/load_demo_system2.sh halt ./sw/c/build/demo/hello_world/demo
Open On-Chip Debugger 0.…
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I try to add the board as described in the Zephyr documentation. But I get a lot of driver errors when compiling the example code. I have created my Device Tree in relation to the implemented drivers …
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Hello.
Thanks to @Dolu1990's advice on SpinalHDL/VexRiscv Gitter, I got Zephyr on Litex/NaxRiscv *bootable* with PLIC interrupt controller.
However, I have the following two issues:
* The console…
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Hi,
I try an application provided by Zephyr `userspace/hello_world_user` on my SoC that i created with LiteX.
```
Configuration :
- OS : Ubuntu 22.04 LTS
- Board : Digilent Arty A7 100T
- L…