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This repository should show how to create awesome documentation for your RTL project using Sphinx.
It should include;
* https://github.com/SymbiFlow/sphinx-verilog-domain
* https://github.com/S…
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It looks like OpenFPGA is already using Sphinx for it's documentation. There are a number of extensions that the SymbiFlow project and Antmicro have been working on to make Sphinx documentation for ha…
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It seems that some of the package are not compatible with the runtime environment present in https://colab.research.google.com/.
Installing the following packages with:
```
!curl -O https://repo…
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### Version
Yosys 0.37+1 (git sha1 e1f4c5c9cbb, clang -fPIC -Os)
### On which OS did this happen?
Linux
### Reproduction Steps
hlblk167_reg
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It would be nice to show how to drive `RGB0PWM` `RGB1PWM` `RGB2PWM` using a clock divider, so achieve the same color cycling effect as the `risc-v` sample.
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The `VerilogSourceFile` and `SystemVerilogSourceFile` need a library attribute, the same as in the VHDLSourceFile. Could you add this to the `HDLSourceFile` class and remove it from the `VHDLSourceFil…
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Sameer , thanks for the great project.
I am relatively new to Verilog and FPGA development, and I find your work in this field particularly inspiring.
Currently, I am encountering some challenge…
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We'd like to allow both SystemVerilog and VHDL test benches in our project. From #297 I learned that
```python
from vunit import VUnit
```
should be used for VHDL, and
```python
from vunit.veri…
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## System information
```
MyHDL Version: 0.12: experimental work on new converter
Python Version: 3.10+
```
I am working on a new converter approach to accommodate future target languages (first …
josyb updated
3 months ago
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Basic idea is to create something low-level, like LLVM Bitcode or WebAssembly, to create the HDL compilers emit the code in this format, which will be fed to the routers/synthesizers after. This will …