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When I run it with one of my toplevel files, git gives this. Where is outvTbgenerator.py
$ python /home/local/NDC/ssheikh/.vscode/extensions/truecrab.verilog-testbench-instance-0.0.5/out\vTbgenerat…
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FPGA world suffers a lot from fragmentation - some tools produce Verilog, some VHDL, some - only subsets of them, creating low-level LLVM-like alternative will help everyone, so HDL implementations wi…
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Hello expert,
**Describe the bug**
The hightlight for " ifdef" "else" "endif“ ”ifndef“ are missing.
- OS: Win 10
- VSCode version version 1.80.1
- Teros HDL : v5.0.2
![image](https://github…
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When trying to run a simulation, a `TypeError` exception is being thrown; error shown below. I was finally able to track down the error to `libpython3.12.so` not being installed, but it would be nice …
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We are at the verge of reaching 50,000 downloads in the marketplace. From this point, I feel it is good to have a structured development plan. The following are a few ideas that I have.
## 1. Suppo…
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@drichmond @mjacobsen
https://github.com/KastnerRG/riffa/blob/master/fpga/riffa_hdl/chnl_tester.v#L128 is only cheating the receiving part. This means **we are not actually using the actual data r…
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The following procedure: https://github.com/hdl/containers/blob/442f15fd80ee5d2935602880c59b6b8ff2077f22/debian-bullseye/vtr.dockerfile#L47-L52
```bash
git clone https://github.com/verilog-to-rout…
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This issue is for bikeshedding keywords.
"def" is introduced as an analog for "wire" in Verilog, albeit more strictly typed (no latches should be inferred when using this). The term "def" for defin…
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It would be helpful if `cocotb.triggers.Timer` could precisely match unit-less verilog delays, which are multiples of the simulator time unit. For instance to write assertions on the value of `q`:
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## System information
```
MyHDL Version: 0.12: experimental work on new converter
Python Version: 3.10+
```
I am working on a new converter approach to accommodate future target languages (first …
josyb updated
4 months ago