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HI,Please allow me to take up a moment of your time.
I'm developing with Vivado of Xilinx and using AXI_Clock_converter IP. Here is my configuration:
![微信图片编辑_20240330105411](https://github.com/alex…
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What is the correct procedure to increase the block ram in lowrisc version 0.2 to run large bare metal applications?
I changed `localparam BRAM_ADDR_WIDTH = 16;` to `localparam BRAM_ADDR_WIDTH = 17;`…
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I have the log2 function defined in a separate "functions.sv" file which is then included in the "config.sv" file only. The "functions.sv" file is not added to the synthesis project but the "config.sv…
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Currently in RapidSmith, there is no `BelType` enumeration to distinguish BELs of a certain type. The current workaround for this is doing a string comparison with the BEL name for what you are lookin…
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Hi,
I have observed that in order to be able to run a different kernel on the AIE it is necessary to both rebuild both the ELF `core.out` and the `.xclbin`. Could you please explain how these two fil…
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Check whether or not following tools support generated CSR modules/RAL packages.
* Simulation
* Cadence Xcelium
* VHDL output
* Mentor Questa/ModelSim
* Aldec Riviera-PRO
…
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Hello, I installed Vivado 2020.2 on a new machine, and tried to get the PMOD AD5 working by following [these instructions](https://reference.digilentinc.com/learn/programmable-logic/tutorials/pmod-ips…
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Dear all,
I want to ask if it is possible to run it on the 3rd party board with the same zynq ultrascale+ fpga core.
due to my limited experience, i need to generate the wrapper file with the zynq p…
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With reference to:
https://github.com/svunit/svunit/blob/84b88033590a1469a238be84d8526b25a9f29d10/bin/runSVUnit#L220C1-L220C96
`xelab` has a tendency to fail quietly when debug is not enabled (m…
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Can you share me more detail about the connection between BRAMs and ZynQ processor?
the System block diagram with BRAMs and ZynQ processor figure in your report is so blur ? thanks so much