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Hello jbilander,
I am new to github, so this may not be the right or best place to get in contact with you. If there is a better way, please give me a hint.
I registered here, because I am cur…
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I would like to use 2 SoC. (e.g one exclusively for WiFi and another exclusively for Data Acquisition) I am able to get 2 Verilog files but am unable to synthesis them due to **Verilog Error: (VERI-12…
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While trying to synthesize the cpu16 project, all my toolchains (xilinx ISE and yosys) choke on this:
```
assign IP = cpu.regs[7];
assign zero = cpu.zero;
assign carry = cpu.carry;
assi…
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## *Repository Creation Request*
Use this to get your experiment repository created or updated on GitHub under Virtual Labs organization.
1. #### Coordinating Institute:IIITH
2. #### Approver’s…
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There do not appear to be any integration tests that exercise the `external_cnf_solver` or `external_aig_solver` commands.
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Hi all,
This is my first time opening an issue on git so pardon me if I miss some things. I compiled icarus Verilog for the M1 Mac and also brew installed gtkwave. I was running a simple Verilog s…
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#### Expected Behaviour
`--enable_timing_computations option` enabled disabling of timing calculations.
#### Current Behaviour
Flag is now removed.
#### Context
`--enable_timing_computa…
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#### Expected Behaviour
Router should route all nets.
#### Current Behaviour
Outputs the warning:
Warning 815554: No routing path found in high-fanout mode for net connection (to sink_rr 125…
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Missing `verilog/gl/gpio_signal_buffering_alt.v`.
`verilog/gl/chip_io_alt.v` is 11 months old and does not have the recent `constant_block` additions.
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I don't think the mode should do that since many people (me included) already have custom keybindings defined for those keys. Afaict, most other major modes leave those keys alone.