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### Description
`mark_last` would take an iterator, and return the iterator zipped with a boolean flag that is `True` only on the last element in the iterator.
### References
I have, at least twi…
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- [x] Disclose initial draft of the methodology and discuss with WG
- [x] Hardware acceleration across silicon architectures (comparing results across _somewhat_ equivalent commercial solutions) http…
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While reading https://spinalhdl.github.io/SpinalDoc/spinal/sim/introduction/, I wondered whether any effort has been done in order to replicate the workflow with VHDL sources. [ghdl/ghdl](https://gith…
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**Type of issue**: bug report | feature request | other enhancement
**Impact**: no functional change | API addition (no impact on existing code) | API modification | unknown
**De…
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Why does OSVVM require multiple libraries for the verification components (I.e. UART has to be in `osvvm_uart` instead of `osvvm` or `osvvm_vc`)? When I quickly glanced through package/file names, I d…
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in rtl/axicb_round_robin_core.sv：
line 114 and line 176, There are two defines of REQ_8
compiler will give error on this
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Add a smoke test script that will:
1. clone aib-protocols github
2. Run a simple case to run these tests in the script
- AXI4-MM dv_simple, AXI4-ST dv_simple
- AXI4-MM DV, AXI4-ST DV
- CA D…
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Hi,
Thank you for sharing this code, it's very informative and useful. I was wondering if you guys had the requirement to do narrow AXI write, if so, what's your solution to do this efficiently?
…
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0.8 DV script runs fixed configuration does not include randomization can you include this please. If you have this script running on Phy2Phy we can use this.
One-text file will address AIB integra…
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[bug_report_example.zip](https://github.com/EttusResearch/uhd/files/6935936/bug_report_example.zip)
## Issue Description ##
Tx Radio randomly deasserts AXI Stream ready signal after some amount of t…