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Hi All!
I'm trying to integrate the L2 InclusiveCache from ChipsAlliance (https://github.com/chipsalliance/rocket-chip-inclusive-cache) with a single Rocket core to be used inside the Litex SoC.
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It seems or1k has an timer object built into the CPU core?
litex has its own timer object.
Figure out the following;
- [X] If the inbuilt or1k timer object is available on real litex SoCs? -- **…
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Hi and thanks for attempting to make something useful out of those old Infrant based NAS.
As those SoCs are based on the LEON (v2, v3 ?) 32bit SPARC architecture, i wondered if anyone ever played w…
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# 总结
- https://github.com/cliffordwolf
- https://github.com/wuxx/icesugar
- https://github.com/icebreaker-fpga/icebreaker
- http://www.elecfans.com/pld/838620.html
cisen updated
3 years ago
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### Version
Yosys 0.24+10 (git sha1 69cbef966, gcc 12.2.0 -march=x86-64 -mtune=generic -O2 -fno-plt -fexceptions -fstack-clash-protection -fcf-protection -fPIC -Os)
### On which OS did this happ…
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Hi esp
I loaded the driver.But there's no device in sight.What's going on?
root@maaxboard8ulp:~/test#
root@maaxboard8ulp:~/test#
root@maaxboard8ulp:~/test#
root@maaxboard8ulp:~/test# insmod es…
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Do you plan to support other FPGA boards in addition to the current Genesys 2?
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Currently, this repo provides a custom systemd service and script (in `examples/passthrough/linux/systemd/`) to load our custom AD1939 and TPA613A2 drivers. This is perfectly functional, but systemd a…
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Generation of bit stream.
` litex-boards/litex_boards/targets/xilinx_ac701.py --build --cpu-type rocket --cpu-variant linux4 --sys-clk-freq 50e6 --with-ethernet`
--> Bitstream generated successfully…
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Hi,
I'm getting started on FPGAs (apologies in advance for noob behavior).
I've bought a Sipeed Tang Primer 20k ( https://wiki.sipeed.com/hardware/en/tang/tang-primer-20k/primer-20k.html ) and I…