-
Currently we generate all the arch.xml files by either;
* Hand using XML includes
* @davesha1's Verilog to arch.xml generator.
As @jhol points out, it would be much easier to generate a lot of …
-
Hi there,
I've tried building from scratch as per the reference document here: https://github.com/jamesbowman/swapforth/raw/master/j1a/doc/j1a-reference.pdf
The Verilog seems to build and program O…
-
All toolchains classes have more or less the same structure / logic with most of the logic residing into `build` method.
It may summarise by:
1. directories creation
2. finalize the design
3. veri…
-
Hi,
I've been trying to get this library to work on an Ice40 FPGA with Icestorm,
it -really- doesn't want to work thanks to the ' or posedge i_SPI_CS_n' of line 154.
On removal, it will compile…
-
I have followed below link to download tool on ubuntu 16.04.
http://www.clifford.at/icestorm/
Where I am facing issue while installing nextpnr as below.
$ cmake -DARCH=ice40 -DCMAKE_INSTALL_PRE…
-
Hi,
I want to configure ice40UP5K's RGB pins as user IOs, similar to what is described in Annex B in TN1288 "iCE40 LED Driver Usage Guide" from lattice and the test code I found on https://github.com…
-
### `brew gist-logs ` link OR `brew config` AND `brew doctor` output
```shell
$ brew config
HOMEBREW_VERSION: 4.3.9-265-g75e77db
ORIGIN: https://github.com/Homebrew/brew
HEAD: 75e77db9f4c5b0760…
-
@mithro says he should do this.
-
Hello,
Why can't we run the verilog code on Radiant Software even though the code is correct? I have been trying to run the code in Radiant Software but it shows design flow errors, why is that?
Tha…
-
The combinatorial LFSR module works perfectly in the following testbench:
```
`timescale 1ns/1ns
`include "../rtl/lfsr.v"
module lfsr_tb();
reg [7:0] data_in;
reg [31:0] state_in;
wire [7:0…