-
When running yosys -p "read_verilog -sv generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.sv"
on my newly generated System Verilog code, after finally extending Yosys for the new syntax…
-
Repro
```
module count_ones (
input logic [4:0] in,
output logic [4:0] out
);
assign out = $countones(in);
endmodule : count_ones
```
UHDM converter doesn't seem to support SV bit vector…
-
**Is your feature request related to a problem? Please describe.**
How to use with verilog/systemVerilog?
**Describe the solution you'd like**
Appears not to function with .v and .sv files. Works…
-
In the latest version of trgen, a grammar that has two or more top-level grammars cannot work without specifying in the desc.xml to pick one.
In [glsl](https://github.com/antlr/grammars-v4/tree/a01…
-
One of the current limitations of the filament language quite severly limits optimization of pipelining. SayI have a component that requires me to instantiate `N` registers, which I will reuse such th…
-
I try to use string localparam in the test case name:
```systemverilog
localparam string NAME = "NAME";
...
`TEST_CASE(NAME) begin
test_fail = 0
`CHECK_EQUAL(test_fail, 0)
end
```
I g…
-
> Note: I'm not sure if this should be an issue or a discussion. I think you can convert between them. Feel free!
I'd like to make two small suggestions to the rule syntax. I realize this is a topi…
-
The `tcb_gpio.sv` RTL is a simple GPIO peripheral with `tcb_if.sv` SystemVerilog interface as the system bus.
`tcb_gpio_wrap.sv` is just a wrapper providing simple signals for ports.
The design wa…
jeras updated
2 years ago
-
The following module verilates fine, works as expected:
```verilog
module InOutMod (input we, inout d);
assign d = we ? 1'1 : 1'bz;
endmodule
```
But put that bad boy inside an interface a…
-
## Steps to reproduce the issue
```
cd tests/svinterfaces
yosys> read_verilog -sv svinterface1.sv
1. Executing Verilog-2005 frontend: svinterface1.sv
Parsing SystemVerilog input from `svinterfa…
pacak updated
2 years ago