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Support for enabling waveform dumping should be added. Different simulators need module parameters passed through in different ways - different command line switches are used, and some require them in…
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- [x] Cheat sheet/language spec (ala Chisel's cheat sheet https://inst.eecs.berkeley.edu/~cs250/sp17/handouts/chisel-cheatsheet3.pdf), Raj
* [magma cheat sheet](https://github.com/phanrahan/magma/b…
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Hello ,
I've cloned the google/riscv-dv repo from github and trying to run one simulation with below command in which I'm getting compilation issue:
Command: python3 run.py --test riscv_arithmet…
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The PDK currently has auto-generated "test" benches for all the standard cells and models. See the following examples;
- https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hd/+/r…
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Verilator has a new feature called "IMPLICTSTATIC warning", when a function is implictly static, in the version v5.006.
When I run the command `make -f $RV_ROOT\tools\Makefile`
The shell print
`%Wa…
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**Describe the bug**
When I click to the Schematic viewer button, the out put is :
2024-03-11 12:53:09.710 [error] Yosys failed.
2024-03-11 12:53:09.716 [info] yowasp-yosys -p "read_verilog -sv …
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Verilator is running my RISC-V processor testbench almost two orders of magnitude more slowly than commercial simulators. I've been told that Verilator is as fast or faster than commercial simulators…
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Hi,
I am trying to verify the ramulator memory controller and DRAM model as explained in the README.
I am using ncsim (ncverilog) as a simulator - ddr4_verilog_models/protected_ncverilog-
I mo…
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I wanted to simulate the core to view wave forms of different instructions. But i am struck. I am getting this error "FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from …
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Hello :wave: Cool project!
I just wanted to ask what is planned for the Verilog generation in the TODO section of the README? I'm a Verilog RTL developer and would be keen to contribute to this pro…