-
**Describe the bug**
I'm running testbenches with sky130 architecture files. When I synthesize a fabric and benchmarks for it, preconfigured testbenches are successfully runned. However when I run fu…
-
### Description
In `libs.tech/openlane/config.tcl` following configuration should be updated.
```
set ::env(GPIO_PADS_VERILOG) "\
$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/verilog/sky130…
-
```python
File /laygo2_workspace_sky130/laygo2_example/logic/inv.py:105
102 print("")
104 # Uncomment for BAG export
--> 105 laygo2.interface.magic.export(lib, filename=ref_dir_MAG_exporte…
-
When trying to import some sky130 gate level verilog, bigspicy fails with:
```
NotImplementedError: Is this supposed to be a disconnection?
```
The problem is a tie cell, in which a disconnect…
-
## Description
PDK `sky130B` broken/missing `libs.ref` and some more files inside `libs.tech` directory.
## Expected behavior
Restore similar structure like `sky130A`
## Environment
`…
-
I got two supply ports in my generated SRAM like this.
```
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
```
When I running MPW flow, I got 8 nets missing in LVS, when I used 4 SRAM ma…
-
The SPICE view in sky130A PDK for sky130_fd_sc_hd stdcells library (sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice) contains diode description with incorrect perimeter value. This result…
-
The SPICE view in sky130A PDK for sky130_fd_sc_hd stdcells library (sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice) contains resistors instantiation with incorrect SPISE syntax. This res…
-
Hello,
I hope my message finds you well.
I am writing to you because i got an error when simulating the bandgap as shown.
Here, I want to describe what i did
1-I generated bandgap_lvs.spice fro…
-
**Describe the bug**
Trying to run the installation as detailed in the documentation. I raised an issue about this yesterday and was said to be solved, but I am having issues still with OpenRAM or Co…