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I am attempting to get the CVA6 APU running on a KC705 board.
What I have done so far:
- Cloned the CVA6 repository, installed the tools and successfully ran smoke-tests.sh
- Ran $make fpga BOA…
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同学你好,我是MaxXing(似乎没什么用的自我介绍环节
发现这个repo是因为之前注意到你fork了Fuxi、YuLang和GeeOS,于是好奇的我就找到了这里。从那以后,这个repo就成为我每天睡前必读的内容了,不看根本睡不着觉(bushi
考虑到Fuxi、YuLang和GeeOS在设计和实现上可能存在许多坑,并且它们的文档也不完全(根本就不存在吧喂),所以这些坑暂时只有我自己清楚。但这样…
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Clash 1.6.4 (and 1.6.3) compiled against ghc 8.8.4 on debian unstable synthesizes verilog fine for my code, but 1.6.4 compiled against ghc 9.0.2 fails on the same synthesis. Same machine, same everyth…
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Hi Jamey,
I'm able to build the tests/ddr3 but I observe that the test doesn't do anything. The test is wrapped in an IF statement which never fires.
https://github.com/cambridgehackers/connectal/bl…
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Hello,
I'm trying the Murax soc on a Tang Nano 9k.
MuraxWithRamInit works with no issues. I'm able to run the demo, and to compile custom C software.
Now I want to try the XIP, to run code from a…
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JTAG and UART Connections:
JTAG Signal | PMOD Pin
-- | --
TMS | JA1
TDI | JA2
TDO | JA3
TCK | JA4
GND | JA5
VCC (trgt) | JA6
UART Signal | PMOD Pin
-- | --
RXD | JA7
TXD | JA8
GND | …
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https://github.com/SChernykh/CryptonightR/issues/1#issuecomment-452775046
> In fact, a carefully designed ASIC could still outperform GPU by spending more resource/area on the bottlenecks. The memo…
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Here's a coherent project plan for Sayma v2. It is informed by extensive discussion on github Issue system over the past year and recent offline discussion with the Sayma v1 developers. This is posted…
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Just wondering, what's the release process for new binaries? I deleted all the release binaries from my last PRs but it doesn't look like a new one has been added in the last few weeks, so the latest …
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@alexforencich I ran stimulus (two AXI Stream interfaces) through the axis_mux.v module and it seems to be missing the tvalid on the first beat on the m_axis output. So, if i transmit send it a trans…