-
This is not a bug, I would just like to discuss some of my findings.
I choose VexRiscv, since it seems to be the the most prominent FPGA implementation of RISC-V.
I did not synthesize VexRiscv mysel…
-
As far as I understand, the [config.json](https://github.com/hanchenye/scalehls/blob/master/samples/polybench/config.json) file has information about the target FPGA (number of DSPs etc) that are used…
-
I'm trying to use this code in a Spartan 6 board, however ISE14.7 does not support System Verilog.
Vivado supports SV but not Spartan 6 family :-(
I tried to translate this code to Verilog but packe…
-
Hi Sergiu,
I get the following error on running c simulation for nnet.cpp in Vivado HLS (windows 10) if I use the testbench directly.:
Couldn't open ref/fc_layer3_py.out@E Simulation failed: Funct…
-
@xbdxwyh i have done the flow upto bitstream generation. after that how i can implement the exported hardware to fpga? i did verified mr chen chen's repo but i cant understand the sdk and petalinux …
-
I have a design where I have imported 2 projects that use common custom circuits. The design simulates and executes ok. When I synthesize the design, I get '"XXXXXX". This is not allowed, please make …
-
Hi authors,
I was trying to replicate your design. I was able to export an IP from HLS 2019.2 and in Vivado 2019.2 while trying to generate a bitstream, it failed with DRC error
[DRC RTSTAT-4] No …
-
-
I'm trying to build `Vitis_Libraries/vision/L2/examples/resize`. Following line does not work on newer GCC versions like `10.2.0`:
https://github.com/Xilinx/Vitis_Libraries/blob/eff2d5dd627c8d6c7ef…
-
My system is Centos 7. My ISE is 14.6 and Vivado is 15.2.
I have already succeeded in generating the bitfile of the project NIC_1G_CML.
Yet I got an error when try to generate the bitfile of referen…