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我在一个新机器上安装这个插件,是安装在vscode远程宿主机上的,发现一运行就报这个错误不知道是为什么
单独下载verible 使用verible-verilog-format是正常的。
`SystemVerilog: Indexing: Unable to process file: file:///data/mxwang/Project/FPGA/ZCU104/wpu_acc_mig_ba…
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### Before start
- [X] I have read the [XiangShan Documents](https://xiangshan-doc.readthedocs.io/zh_CN/latest). 我已经阅读过香山文档。
- [X] I have searched the previous issues and did not find anything rel…
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### Verilator Simulation Warnings
While running the synthesis for the [OPL3 FM Synthesizer,](https://github.com/gtaylormb/opl3_fpga) I encountered several warnings related to the RTL code. Although…
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### Motivation
For compatibility purposes, ROHD currently does per-element assignments between arrays. A common case of assignment between two entire arrays of the same dimensions makes many more li…
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On 11/03/2020 15:19, Aleksander Czechowski wrote:
This repo is for learning in games, which are sort of generalized RL environments.
You need to compile it first, but by following the instructions…
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Issue Type: Performance Issue
After using extension bisect, I found that this extension is slowing down vscode's Ctrl+P. Not sure what other information I can provide at this time. Let me know.
…
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Hi,
All my module instantiation in my old code got error: "Unknown module type" after the update.
Simulation and synthesis by vcs and vivado still work.
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I have taken a quick look into supporting the Synopsys VCS simulator.
It looks like similar to Cadence's `cds.lib`, VCS needs a file `.synopsys_vss.setup` for the library name-to-path mapping. http://…
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I'm reading the KMD and UMD source code , but dosen't find the entrance or call to SystemC model. So could anyone tell me what the role the SystemC model play?
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Hi, thanks for the good work!
Maybe I missed something, but I couldn't find an example of how to initialize a register value:
```veryl
pub module RegisterFile (
i_clk: input clock,
) {
v…