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### Why did we need this? (what does this change enable us to do)
This is a temporary performance enhancement that allows to disable the check_route routine in several VPR steps (routing and genfas…
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I am trying to use pyverilog with the register files generated with peakRDL-verilog (https://github.com/hughjackson/PeakRDL-verilog) and I am getting the following error.
g++ -I. -MMD -I/usr/loca…
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https://github.com/cucapra/calyx/pull/847 attempted to enable parallel assignment checking with the icarus backend but inadvertently made all tests fail (another argument for #755). The problem is tha…
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It would be nice to expose `SB_LEDDA_IP` (as in https://github.com/im-tomu/foboot/blob/master/hw/rtl/sbled.py#L93) to the verilog and litex samples, so that developers going thru the workshop can do m…
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Al exportar a verilog un bloque de memoria, se crea un parámetro con tipo "archivo" pero el archivo con los datos no és creado.
En los archivos adjuntos:
El bloque "Cadena" genera una línea de ver…
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# SymbiFlow Formal Verification
Next semester I am doing an independent study on formal verification and am planning on doing a project involving SymbiFlow. My initial thought is performing formal …
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As discussed in the [issue](https://github.com/jacktasia/dumb-jump/issues/240), jump to define works if it is invoked from a "sv" file. But it fails when invoked from a verilog file (ext "v"), as it i…
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I used the automated make script to generate a Vivado project for FPGA implementation of Vortex. It creates the project however gives error during synthesis:
> [Synth 8-2671] single value range is …
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Simulator: Modelsim
Tb connection:
axi4lite-master-bfm axil_adapter axil_ram
In simulation I found error:
**" ** Fatal: (vsim-3373) /home/peio/fpgawork/cores/verilog-axi/rtl/axil_adapter_w…