-
If we used the 6 bits in width to xor the 6bit value that feeds the `signal_` value, we can let the users create sounds that are considerably more interesting.
As simple as something like this: (pl…
-
The hack to poke an internal verilog signal corresponding to a coreir register no longer works: https://github.com/leonardt/fault/blob/master/fault/wrapper.py#L141-L147
Need to refer to the generat…
-
It seems that some of the package are not compatible with the runtime environment present in https://colab.research.google.com/.
Installing the following packages with:
```
!curl -O https://repo…
-
At the moment, it seems Logisim-evolution is only supporting target FPGA synthesis tools from Xilinx and Intel (Xilinx ISE, Xilinx Vivado, Intel Quartus Prime). The low-cost, open-source TinyFPGA BX b…
-
First, let me say this project looks great!
Does anyone know if N. Wirth looks at this repository? Is this done in cooperation with him, or just according to his license? Would changes here get abs…
-
The Logisim and Verilog portions of the project should be cleaned.
For Logisim remove circuits not connected to anything
(there is a bit extender in used), also lots of probes in the IC's
For …
-
Question: how do you handle relating error messages to the original systemverilog source code?
Like, an issue I find with using generators (of which, this project is generating verilog, given syste…
-
Hi,
I'm using the latest build of Yosys 0.9+932 (git sha1 f8d5920a, gcc 7.2.0-8ubuntu3.2 -fPIC -Os)
I'm attempting to read a cell library, which contains a cell like this:
```
`celldefine
m…
-
In system verilog, I usually write things like `logic [2:0] [1:0]`, and I'm wondering is that possible for RustHDL.
-
Hi!
What FPGA unit did you use to run and test the Verilog codes? Because this design contains 1767 I/O ports.