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I build TCP-server from docker container, but it shows "panda: disagrees about version of symbol module_layout"
https://pandablocks.github.io/main/developer/how-to/run-container.html
It means roo…
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when i follow the SOP to build bitstream, it occurs:
```
java.lang.reflect.InvocationTargetException
at ... ()
at starship.utils.stage.FIRRTLGenerator$.$anonfun$elaborate$2(Rocke…
wisen updated
3 months ago
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DPU kernet driver not working for Vitis-AI 3.0 in petalinux 2022.2 project.
Adding the three CONFIG_vitis-ai-library* packages to project per instructions here:
https://github.com/Xilinx/Vitis-AI/…
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> Thank you for reporting a bug!
Everyone loves complaining about bugs, so that's easy to do
> In order to be able to resolve your issue as fast as possible, please provide us with the version …
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this thread is about collecting clue on externally clocking HAL threads.
There is huge upside in having support for this, as it would allow hardware to sample positions in next-to-exact time and then…
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A few times, I was asked about the feasibility of building something similar to a very low latency PID like [FALC-PRO](https://www.toptica.com/products/laser-rack-systems/laser-locking-electronics/fal…
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I am pondering how to think about packet rates in the 100G era. How should we be designing and optimizing our software?
Consider these potential performance targets:
- A: 1x100G @ 64 Mpps.
- B: 1x100…
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I am trying to use LitePCie for my project with the [Trenz TE0712](https://wiki.trenz-electronic.de/display/PD/TE0712+TRM) board. The target and platform files are not there in the [litex_boards](http…
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When I used the makefile in `fpga` subdir, I got an error.
```sh
➜ fpga git:(main) make build
rm -rf /home/zfl/workspace/AnTiQ/fpga/build /home/zfl/workspace/AnTiQ/fpga/reports/240116_194056_ut…
zflcs updated
3 months ago
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![image](https://user-images.githubusercontent.com/31478831/173376128-f263904a-84d2-4757-af0a-718110e4b26c.png)
Hello,
I did all step successfully, but when I generated the bitstream, I have the…