-
-
Getting logical nets out of Yosys is more tricky, we might need to examine cell connections.
The current implementation return wires, but a net may consist of multiple wires.
-
### Feature Description
As of yosys-0.37 at least, using "inout" in a modport yields
```
ERROR: syntax error, unexpected TOK_INOUT, expecting TOK_ID or TOK_INPUT or TOK_OUTPUT or ')'
```
Is this …
-
I used the method axidma_oneway_transfer() to individually write a 1024 bytes of data and then read a 1024 bytes of data, and the result is what I expected.
But when I write a 1024 bytes data with th…
-
** Which tutorial are you running? **
https://github.com/Xilinx/Vitis-Tutorials/blob/2022.2/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z/05-RPU%20version%5Boptional%5D.md
** Describe the …
-
The following Vexriscv configuration hangs when you try to run on the board:
`generate+bypass:false+csrPluginConfig:mcycle+dCacheSize:0+hardwareDiv:false+iCacheSize:8192+mulDiv:false+prediction:non…
-
### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
When I was running my own C++program, the output printed through the printf() function …
-
Looks like half the work is done: https://github.com/SymbiFlow/prjuray/blob/3f5736237309e0670b4351f39fad8b4bd9cb6dd0/tools/dump_features.tcl#L646
but this isn't actually appearing in the databases …
-
Files support a few standard attributes like file_type and is_include_file but there are use cases thatI believe would be best served by custom attributes that are only valid for certain file types an…
-
I want to modify your code so that it could take hls::stream& instead of hls::stream&
i.e from
void canny_edge_detection(stream& axis_in, stream& axis_out,
uint8_t& hist_hthr, uint8_t& hist_lth…
3togo updated
5 years ago