-
Info:['-b''--board'] is deprecated,
Info:['-t',--top-module'] isdeprcated. Info; Project has no apio.ini File
-
Currently ``apio time`` is not implemented for the ECP5 and Gowin families. This issue is for implementing them.
Timing verification is important to confirm that the synthesized code is within the…
zapta updated
1 month ago
-
I seem to have found an infinite loop in the GUI code, or at least pathological slowness that fails to un-freeze the GUI after 30 minutes at 100% CPU. This does not require a loaded design.
To repr…
-
If I perform the following steps, everything builds ok using trellis, and I get the BIOS prompt.
```
cd litex-boards/litex_boards/targets
./radiona_ulx3s.py --build --device=LFE5U-85F --cpu-type=ve…
-
I can't get things to compile for the ecp5 architecture.
I am using a recent (last week or so) build of oss-cad-suite to do the synthesis. synthesising fails with the following error message:
`…
-
Hi !
Filing this to report that I've been able to get this to work on the ULX3S board (based on Lattice ECP5, 12K gates).
Due to compile issues with the open source toolchain of the ULX3S, I en…
-
Adding/Finishing ECP5 support would be interesting since could provide a FOSS solution (Core + Toolchain) for a SATA controller and would also be directly useful for projects like [Linux-on-LiteX-VexR…
-
Lattice ECP5 and MachXO3 works very well with openFPGALoader. How can I help to add support for the Lattice ECP3? I thought it is the "same" as ECP5, but maybe not. At least I can help in testing...
-
Branch and add support for ECP5-85.
-
The yosys suite supports the ECP5 family of FPGAs, would the Reduceron work with such a combination?
A quick glance at the Cyclone IV says the max gate count is about 150,000.
The ECP5 gets as lar…
shapr updated
4 years ago