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Hello,
During my experiments with the Chipyard FFT generator, I noticed that your lab has also experimented with the Genesys2 for on-board testing. We referred to your Genesys2 code, but encountere…
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I would like to use IPBus on a Digilent Genesys2 evaluation board. It uses the same FPGA as the KC705 but would require an RGMII interface to the PHY. I can see that each of these is used by different…
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### Is there an existing core-v-mcu bug for this?
- [X] I have searched the existing bug issues
### Bug Description
Hello there,
I've been working on core-v-mcu for a little bit of time. I'm cur…
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### Is there an existing core-v-mcu bug for this?
- [X] I have searched the existing bug issues
### Bug Description
I attempted to run the application on the Genesys2 board in the quickstart folder…
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Due to the IO changes, there isn't a valid IO assignment for the Gensys2 board available. If that has been fixed we can try to re-enable the FPGA target.
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Hello everyone,
we are working on the genesys2 board and want to use the cva6 core. Right now, we are setting up our development environment and for that we need a u-boot with a working Ethernet. W…
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### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
hajra@merledu1:~/ariane$ make fpga
make -C corev_apu/fpga/src/bootrom BOARD=genesys2 X…
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hello,
when I cd litex-boards/litex_boards/targets/, and python digilent_genesys2.py,
then info error below:
Traceback (most recent call last):
File "/home/fso/LiteX/litex-boards/litex_boa…
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Can I use these lowrisc-nexys4ddr bit files for genesys2 fpga board as it is? If yes then how can I use that or any modifications are needed?
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Hello community,
I've been trying to synthesize the vicuna vector coprocessor for Kintex7 FPGA (Genesys2 Board).
Wherein I've created a **_vproc_config.sv_** package file using command -
make …