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fpgaminer_top.v
you have a long compare each time round the loop
// Stop hashing if we've run out of nonces to check
else if (nonce2 == 32'hFFFFFFFF)
modify nonce2 to make it 1 bit longer, …
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Hello! Thanks for your repositories first! I have a board=xc7k325tffg900-2(as the same as BOARD=kc705). However, it is RGMII for the ethernet on my board. (I have deleted the ethernet and then success…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched the [documentation](https://chipyard.readthedocs.io/)
### Fe…
zzulb updated
8 months ago
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Hello Serge,
You have done great work in this project. I really appreciate it. However, I am now stuck in the simulation step of kc705 testbench. I followed these steps to simulate it. I have gone to…
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Hi, I followed the instructions and successed with the command "make core BOARD=kc705". But when I ran make BOARD=kc705, I had the following errors. Please help me figure out what is wrong. Thanks.
…
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i am implementing Pulissimo project SoC on FPGA. I use Zedboard. I got an error when trying to use openocd to conig jtag for debugging. Please follow the instructions in the readme [https://github.com…
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Thanks for your greate job, i hope the project to support xilinx kc705 pcie2.0.
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PoC currently provides only an [adapter](https://github.com/VLSI-EDA/PoC/blob/release/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl) which maps between the PoC.Mem interface and the native interface …
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I'm running Mint Linux 19.2, and I used the apt get method to install the fpgamake software on my machine.
One of the first steps I am trying is to build an example project, but I'm not able to, it s…
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Hi, I am working on the hello world test of "lowrisc-chip". The branch that I am working on is kc705_update. The problem is that I can generate the bitstream file and combine it with the "hello world"…