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Hi. I succses used this project with a little bit modifications for 10G ethernet kintex7. Now I want to apply ip ten_gig_pcs_pma_0.xci for ultrascale. The specification PG068 states that I should use…
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I am trying to implement your project on a third-party FPGA based on kintex ultrascale xcku060.
The project can successfully pass synthesis and implementation stages after the xdc file is modified pr…
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Hello,
### Issue Description:
There are a few critical warnings which I believe could be solved relatively easily.
A lot of the critical warnings present on the vivado.log file are related to…
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Hello,
I'm wondering if parts of this project can be used to control the Xilinx soft PCIe PHY ([PG239](https://www.xilinx.com/content/dam/xilinx/support/documentation/ip_documentation/pcie_phy/v1_0…
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I have adopt about different IO standard.
MIPI CSI 2 has 200mv swing voltage at HS mode**(SLVS200)**
but, is it possible to capture these low voltage differential signal with FPGA?
I think th…
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之前装了Vivado2020.2，现在需要装2017.1，是从博客园看的攻略，怕博客园倒闭了，在这里记录一下
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Hi:
Sorry to bother you again.
This time i am using the cam module , but i found some of the ports are being unspecified, so i want to know is there any timing specifying of the ports of cam.v…
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自己2012年开始接触FPGA，那个时候最希望的就是有一个自己的FPGA板。后来在FPGA课程老师的帮助下，申请了一个学校项目，利用项目经费自主设计了一个cyclone iii开发板。
虽然板子设计的比较丑，但至少有自己的FPGA板了。后来利用这个FPGA板，自己完成了本科毕业设计，还顺便获得一个学校优秀毕业设计。
研究生以后，导师有充足的经费，买了功能更强的板子，自己设计的FPGA板也就成为…
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## Expected Behavior
It should be possible to open the elaborated design with port_sgmii_gtx_X0Yx included in the block design.
## Current Behavior
Opening the block design fails with…
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First of all, thanks for the great work with NaxRiscv! With your howto I was able to launch Debian on latest LiteX with 175 MHz dual core NaxRiscv and 1MB L2 cache on Alinx AXKU040 board (Kintex Ultra…