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This reproduces in 3.480 and I don't see any related code changes in the 3.483 version. Continuous assignments in an interface cause a missing method error for new_contassign which exists on Verilog::…
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### TODO
We have a new .cdl netlist for the GPDK 45 but we need to set up a new parser for it.
- Create basic parser in DesignDB for even processing the new file format (PyParser)
- Create a new …
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Design is missing in edif netlist parser. This make is so that the top_level_instance has a hard coded "top" name as opposed to whatever was defined in the original....
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It would be nice to have an output and/or input for some form of EDA type netlist, whether in SPICE type format, Protel/Altium format, Kicad format, eagle format, etc.
If people want this feature…
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### Describe the bug
when reading multiple def files using 'read_def -child', warnings get written to defRWarning.log
1) But this file get's overwritten by each new read_def, so one only get's the…
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When trying to convert a much larger design, I encountered this error:
```
Traceback (most recent call last):
File "IFsupport/IF2bookshelf.py", line 586, in
if_parser = IF2bookshelf(bookshe…
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Python 3.12.2, with lcapy 1.23
# Problem
I may not see a voltage source that is short-circuited or all other concerns regarding this error, but I cannot figure out why this configuration is not so…
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a user [reported](https://sourceforge.net/p/qucs/discussion/311050/thread/88a53c86/) that `qucsator` does not work (anymore) with the input netlist coming from `stdin`.
At a first glance it seems t…
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version: 0.1.0-next.711c68e
https://cloud.monostable.co.uk/component_tester.net
```js
const {netlist} = require('libkicad')
const fs = require('fs')
const n = netlist.parse(fs.readFileSync(…
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#### Expected Behaviour
We should have no compiler warnings.
#### Current Behaviour
Some warnings in vqm2blif:
[ 50%] [BISON][VqmParser] Building parser with bison 3.8.2
/home/runner/work/vtr…