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## Project Documentation & Links
Project Name: RocketChip
Project Repository: https://github.com/chipsalliance/rocket-chip
Project Data File/PR: https://github.com/chipsalliance/tac/blob/main/project…
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### Before start
- [X] I have read the [XiangShan Documents](https://xiangshan-doc.readthedocs.io/zh_CN/latest). 我已经阅读过香山文档。
- [X] I have searched the previous issues and did not find anything releva…
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#### Before start
PLEASE MAKE SURE you have done these:
- [x] (Select what you have done like this)
- [x] I have read the [RISC-V ISA Manual](https://github.com/riscv/riscv-isa-manual) and th…
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**when i build verilog, i got the error as follows:**
rocket-chip/src/main/scala/amba/axi4/Credited.scala:12:64: not found: type Parameters
[error] class AXI4CreditedBuffer(delay: AXI4Credi…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- […
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**Type of issue**: question
Why does my scalaVersion use the default setting 2.13.10, but when testing boom core, it reports the following error, claiming it cannot find the rocketchip_2.13-1.6.0…
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> FastVDMA was verified in the xc7z030fbg676-2 chip
hi, is Fastcdma tested on rocketchip?
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Hello, I am attempting to configure a NOC within Firesim version 1.18.0 by utilizing rerocc, with a configuration featuring 5 Rocket cores and 10 Gemmini accelerators. Despite having successfully gene…
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`make compile` fail for commit 5994344ba065f160011531ad7dda6b85615fee66(previous commit 41150ae44ff1f83fb756aa2d23f64a8ab963ee7c not fail), below is some related log:
```
[#03] [error] /home/ycy/b…
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Hello everyone!
When I am trying to build the project I get the following error:
```
1 targets failed
emulator[freechips.rocketchip.system.TestHarness,freechips.rocketchip.system.DefaultConfig].ge…