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FPGA-MAFIA
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fpga_mafia
Designing a Multi-Agent Fabric Integration Architecture to run on de10-lite FPGA.
MIT License
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*.qsf file update
#641
roman012285
closed
1 month ago
0
Design `mem_ss` to work with SDRAM controller and D_CACHE
#639
roman012285
opened
1 month ago
0
Sdram controler for read/write 8 length bursts
#638
roman012285
closed
1 month ago
0
working SDRAM controller
#637
roman012285
closed
1 month ago
0
fpga test sdram controller
#636
roman012285
closed
1 month ago
0
write FSM to test bursts in random addresses and banks
#635
roman012285
closed
1 month ago
0
keyboard basic test design
#633
roman012285
closed
2 months ago
0
set timing parameters in *.sdc file
#632
roman012285
closed
2 months ago
0
comment clear_screen funtion to avoid timeout
#631
roman012285
closed
2 months ago
0
start debug keyboard
#630
roman012285
closed
2 months ago
1
fix sdram_ctrl issues - wrong PIN assignment in *.qsf
#629
roman012285
closed
2 months ago
1
Nr cpu ex #553
#628
roman012285
closed
2 months ago
0
Test and debug KBD on fpga
#627
roman012285
opened
2 months ago
0
[big_core][defines]#600: Add VGA CounterX and CounterY to CR space for timing
#625
NoamRahat
closed
2 months ago
6
Jacob - Write a combined weekly for WW14-15-16
#624
amichai-bd
closed
1 week ago
0
Noam - Write a combined weekly for WW14-15-16
#623
amichai-bd
closed
1 month ago
0
several updates to graphic_vga.h
#622
jacobavitan837
closed
2 months ago
0
`core_rrv` has been renamed to `big_core` - ONLY READ ISSUE
#621
roman012285
closed
2 months ago
4
rename core_rrv into big_core
#620
roman012285
closed
2 months ago
0
refactor and debugging sdram controler
#619
roman012285
closed
2 months ago
0
Rename core_rrv to big_core
#618
roman012285
closed
2 months ago
0
start debugging sdram controller on FPGA
#617
roman012285
closed
2 months ago
0
finish design sdram_ctrl (draft version) + basic TB. Supports only single read and writes
#616
roman012285
closed
2 months ago
0
refactor and debug init state
#615
roman012285
closed
2 months ago
0
Refactor the CR structure in the core_rrv
#614
amichai-bd
opened
2 months ago
0
write system verilog for INIT state - without debug(passed -hw)
#613
roman012285
closed
2 months ago
0
refactor and change coding style
#612
roman012285
closed
2 months ago
0
writing MC (memory controller) for communication between host and SDRAM
#611
roman012285
closed
1 month ago
1
integrate sdram to MAFIA
#609
roman012285
closed
2 months ago
1
debug and fix state machine - works!
#608
roman012285
closed
3 months ago
0
add sdram state machin
#607
roman012285
closed
3 months ago
0
rename sanity with level2
#606
amichai-bd
closed
3 months ago
1
add *.qws quartus generated file to git ignore
#605
roman012285
closed
3 months ago
0
first draft of sdram tests
#604
roman012285
closed
3 months ago
0
Abd create unit script
#602
amichai-bd
closed
3 months ago
1
update SDRAM_RTL_TEST folder with new IP version
#601
roman012285
closed
3 months ago
2
Add the VGA CounterX CounterY to the CR space so its accessible from timing
#600
amichai-bd
opened
3 months ago
1
3 stage pipe line core
#599
roman012285
closed
3 months ago
0
Mini core rrv fix bugs and add tests
#598
roman012285
closed
3 months ago
0
Mini core rrv
#597
roman012285
closed
3 months ago
0
adding all instructions, and ref_model to tb.
#596
roman012285
closed
3 months ago
0
Using the FPGA of-die memory, sdram | Create a POC
#595
amichai-bd
closed
2 months ago
2
add d_mem and forwarding unit
#594
roman012285
closed
3 months ago
0
fix bugs and add tracker
#593
roman012285
closed
3 months ago
0
update the letters font
#592
jacobavitan837
opened
3 months ago
0
New regress for core_rrv -> level0_no_ref
#591
amichai-bd
closed
3 months ago
0
Jacob branch
#590
jacobavitan837
closed
3 months ago
0
qws file
#588
roman012285
closed
3 months ago
0
3 stage cpu design based on MAFIA codinf style
#587
roman012285
closed
3 months ago
0
Jacob branch PS2_GCD
#586
jacobavitan837
closed
3 months ago
6
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