KestrelComputer polaris issues

KestrelComputer / polaris

RISC-V RV64IS-compatible processor for the Kestrel-3

Mozilla Public License 2.0

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issues

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README.md: Make subdirectory links clickable

#29 neuschaefer opened 1 year ago
0
Introduce bottleneck as an official core

#28 sam-falvo closed 7 years ago
0
Make boot ROM contents configurable through top-level parameter

#27 olofk closed 7 years ago
3
Reorganize repository.

#26 sam-falvo closed 7 years ago
0
Missing bus error signals on D port

#25 sam-falvo opened 7 years ago
0
Missing bus error signals on I port

#24 sam-falvo opened 7 years ago
0
Repair Github formatting

#23 sam-falvo closed 7 years ago
0
Support SLT/SLTU instructions.

#22 sam-falvo closed 7 years ago
0
Complete Example chapter.

#21 sam-falvo closed 7 years ago
0
Documentation of example application WIP

#20 sam-falvo closed 7 years ago
0
Evaluate: Migrate testbench code to verilator?

#19 sam-falvo closed 7 years ago
1
KCP53000 currently lacks SLT and SLTU functionality.

#18 sam-falvo closed 7 years ago
0
Fix Verilog so unconnected pins are explicit.

#17 sam-falvo closed 7 years ago
0
Support external interrupts.

#16 sam-falvo closed 7 years ago
0
Table formattings broken in ISA doc

#15 The-Blue-Wizard closed 7 years ago
1
Provide example instantiation of CPU in data sheet documentation.

#14 sam-falvo closed 7 years ago
1
Interrupts not yet supported.

#13 sam-falvo closed 7 years ago
0
mstatus.HPP refers to M-mode, not H-mode.

#12 sam-falvo closed 7 years ago
0
mimpid fields are statically assigned by a programmer.

#11 sam-falvo closed 7 years ago
1
mimpid register identifies as 116100801; change to 2016101600.

#10 sam-falvo closed 7 years ago
1
Data sheet. WIP but incrementally complete.

#9 sam-falvo closed 7 years ago
0
M-mode only design is not scalable to better CPUs. Use U-mode only design.

#8 sam-falvo opened 7 years ago
1
K3UG needs chapter or appendix for simplified CPU datasheet.

#7 sam-falvo opened 7 years ago
0
Datasheet required for Forth Day/RISC-V workshops.

#6 sam-falvo closed 7 years ago
0
Clean up module interface.

#5 sam-falvo closed 7 years ago
0
Instruction fetch bus exposes ISIZ_O signal pair, but it'd be simpler to expose ISTB instead.

#4 sam-falvo closed 7 years ago
0
Polaris 116080201 is too slow.

#3 sam-falvo opened 7 years ago
1
Polaris. The 64-bit, M-mode only RISC-V CPU.

#2 sam-falvo closed 7 years ago
0
Forgot to merge from when I was on vacation.

#1 sam-falvo closed 7 years ago
0