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SpiNNakerManchester
/
spio
A library of FPGA designs and re-usable modules for I/O and internal connectivity in SpiNNaker systems.
BSD 3-Clause "New" or "Revised" License
6
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Add additional peripheral routing entries
#45
lplana
closed
1 year ago
0
Update peripheral support
#44
lplana
closed
2 years ago
0
Update peripheral support
#43
lplana
closed
3 years ago
0
update pin SLEW settings
#42
lplana
closed
2 years ago
0
power and ground issues in FPGA0
#41
lplana
opened
3 years ago
0
Fix packet store ba pointer bug
#40
lplana
closed
3 years ago
0
packet store goes empty incorrectly
#39
lplana
closed
3 years ago
0
changed license to BSD 3-clause.
#38
lplana
closed
5 years ago
0
New stac config
#37
lplana
closed
5 years ago
0
STOP register should also stop incoming packets
#36
lplana
opened
7 years ago
0
sender deadlock recovery mechanism could be useful
#35
lplana
opened
7 years ago
0
packet loss in design raggedstone_spinn_aer_if
#34
lplana
closed
7 years ago
1
Concurrent accesses to a bmp can cause crash
#33
lplana
closed
7 years ago
0
Code cleanup
#32
lplana
closed
7 years ago
0
Review dump mode on SpiNNaker-AER interface on RaggedStone2 board
#31
lplana
opened
7 years ago
2
Control aer if
#30
lplana
closed
7 years ago
0
Added a new design that implements a SpiNNaker <-> AER interface.
#29
lplana
closed
7 years ago
0
Uncommented note in "spinnaker_fpgas_reg_bank.v"
#28
gengtingliu
closed
8 years ago
1
Param ctrl
#27
lplana
closed
8 years ago
0
Explicitly state BMP version requirement in README.
#26
mossblaser
closed
8 years ago
2
Psync snd rcv ft
#25
lplana
closed
8 years ago
1
Updated the SpiNNaker Link README.md file
#24
lplana
closed
8 years ago
2
Allow disabling and tristating of individual 2-of-7 links
#23
mossblaser
closed
8 years ago
1
"STOP" register
#22
mossblaser
closed
8 years ago
1
Missleading comments in "spinnaker_fpga_top.v"
#21
gengtingliu
closed
8 years ago
1
Packet counter not listed as dependency for top level module for SpiNNaker FGPA design
#20
gengtingliu
closed
8 years ago
1
Idle Packet Scrambling
#19
mossblaser
closed
9 years ago
0
SPI Logic Should Run at Periph's Clock Rate
#18
mossblaser
opened
9 years ago
2
Add SPI interface to SpiNNaker FPGAs for BMP-driven debug.
#17
mossblaser
closed
10 years ago
1
Add parameter to select position of North/South Links
#16
mossblaser
closed
10 years ago
0
Per-FPGA image
#15
mossblaser
closed
10 years ago
0
Make SpiNNaker front/back connection swap parameterisable.
#14
mossblaser
closed
10 years ago
1
Verify Raggedstone FTDI design UART buffer size choice.
#13
mossblaser
opened
10 years ago
1
Remove b2b_usrclk_i aliases (and friends)
#12
mossblaser
opened
10 years ago
1
Use BMP signal to reset SpiNNaker FPGAs
#11
mossblaser
closed
10 years ago
1
What to do when peripherals but no board-to-board links are connected
#10
mossblaser
closed
2 years ago
3
Peripheral timestamp Awareness
#9
mossblaser
opened
10 years ago
1
Peripheral Emergency Routing Awareness
#8
mossblaser
opened
10 years ago
1
Add parameter to disable ring network and peripheral links for SpiNNaker design.
#7
mossblaser
closed
8 years ago
1
Frame Assembler/Disassembler don't support rdy/vld at any time
#6
mossblaser
opened
10 years ago
10
Raggedstone press-to-send demo stops working.
#5
mossblaser
closed
10 years ago
3
Don't assert signals halfway through a cycle in speed doubler.
#4
mossblaser
closed
10 years ago
1
Remove clock correction insertion/removal from frame assembler.
#3
mossblaser
closed
8 years ago
1
Hot re-plug fails for SpiNNaker boards.
#2
mossblaser
closed
8 years ago
1
spio_hss_multiplexer_tx_control drops 32-bit words when inserting clock correction sequence.
#1
mossblaser
closed
10 years ago
0