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Xilinx
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finn
Dataflow compiler for QNN inference on FPGAs
https://xilinx.github.io/finn
BSD 3-Clause "New" or "Revised" License
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218
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Compiler Difference Between W1A1 and W4A4
#1031
Ba1tu3han
opened
3 months ago
2
Fix RoundAndClipThresholds Transformation
#1030
iksnagreb
opened
3 months ago
4
Update visualization.py
#1028
kaycoemert
opened
3 months ago
0
Release merge for v0.10
#1024
auphelia
closed
3 months ago
0
Minor fixes to documentation and examples for dev branch
#1023
auphelia
closed
3 months ago
0
Extension to end2end mobilenet test
#1022
mmrahorovic
closed
2 months ago
0
VVU estimation function fixes
#1018
mmrahorovic
closed
3 months ago
0
Extract Thresholding RTL RAM trigger attributes to folding config
#1016
azizb-xlnx
closed
3 months ago
0
[Tests] Force HLS components for special case cnv-2-2 on u250 and pyn…
#1015
jmonks-amd
closed
3 months ago
0
RTL SWG CPPsim
#1014
mmrahorovic
closed
3 months ago
0
VVAU renaming and disabled resType selection in convert-to-hw
#1012
mmrahorovic
closed
3 months ago
0
[Thresholding RTL] Prepend dummy threshold for narrow range quantization
#1010
azizb-xlnx
closed
3 months ago
0
Disable unsigned weights RTL MVU
#1008
mmrahorovic
closed
3 months ago
0
[Thresholding rtl] Update template wrapper file names to match top module name.
#1006
azizb-xlnx
closed
3 months ago
0
Fix to default to HLS MVAU if bit-width < 4
#1005
mmrahorovic
closed
3 months ago
0
Broadcast single threshold values along PE dimension
#1002
azizb-xlnx
closed
3 months ago
0
Refactoring of RTL VVAU
#1000
mmrahorovic
closed
3 months ago
0
StreamingFIFO count width mismatch between Python and RTL
#998
lecramdev
closed
2 months ago
2
[QONNX] update to latest main
#997
azizb-xlnx
closed
3 months ago
0
Accuracy Discrepancies between the built Accelerator (68%) on ZCU102 and Brevitas Model (86%)
#996
shakeelakram00
opened
4 months ago
3
Refactoring of RTL MVAU
#995
mmrahorovic
closed
3 months ago
0
OPSET and Assuming 4D input is NCHW
#993
Ba1tu3han
closed
5 hours ago
0
4 - Full accl support
#990
ADGLY
opened
4 months ago
0
Add C++ driver support
#989
LinusJungemann
opened
4 months ago
1
Fix: Add stream padding to RTL SWG
#983
fpjentzsch
closed
4 months ago
1
Bugfix to MVAU refactored op
#980
mmrahorovic
closed
4 months ago
0
Bugfix/pynq driver alveo
#979
jmonks-amd
closed
4 months ago
1
Clipping thresholds to input range + 1?
#978
iksnagreb
opened
4 months ago
4
Refactoring of RTL MVAU/VVAU ops
#977
mmrahorovic
closed
4 months ago
0
[MVU/VVU] Support for double-pumped DSPs
#976
mmrahorovic
closed
4 months ago
0
Support for multi-packed DSP58s for VVUs
#975
mmrahorovic
closed
4 months ago
0
Refactoring of RTL MVAU/VVAU ops
#974
mmrahorovic
closed
4 months ago
0
Refactoring of RTL MVAU/VVAU
#972
mmrahorovic
closed
5 months ago
0
Refactoring of HLS MVAU/VVAU
#971
mmrahorovic
closed
5 months ago
1
Feature/packaging
#970
azizb-xlnx
opened
5 months ago
0
Bugfix/fifo sizing tests
#969
jmonks-amd
closed
5 months ago
0
Refactor/threshold rtl
#968
azizb-xlnx
closed
3 months ago
0
WIP: Non-Interactive Docker Run
#967
iksnagreb
opened
5 months ago
0
[Deps] Add "pyyaml==6.0.1" dependency to Dockerfile
#966
iksnagreb
opened
5 months ago
0
Enable analysis report of post synthesis resource utilization in json
#965
iksnagreb
closed
2 months ago
0
Refactor Thresholding HLS Variant only
#964
azizb-xlnx
closed
5 months ago
0
Refactoring of MVAU and VVAU
#963
mmrahorovic
closed
5 months ago
2
Can't find 'MatrixVectorActivation_0_wstrm' IP
#961
ppccww0201
closed
5 months ago
1
Jenkins pipeline improvements
#959
jmonks-amd
closed
5 months ago
0
Feature/fifo sizing behaviour
#958
jmonks-amd
closed
5 months ago
0
Add optional env var to skip board download
#956
jmonks-amd
closed
5 months ago
0
cycle-free graph violated
#955
ppccww0201
closed
5 months ago
3
ConCat layer Issue
#954
pkdeep
closed
3 months ago
4
Add support for multi FPGA builds
#952
cantbeblank24
opened
5 months ago
0
3 - Add support accl
#950
ADGLY
opened
5 months ago
0
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