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yosys
Yosys Open SYnthesis Suite
https://yosyshq.net/yosys/
ISC License
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Prepend Verilog globals to module AST
#4656
jmi2k
opened
1 month ago
2
cxxrtl: fix vcd writer scope handling
#4655
rroohhh
closed
1 month ago
0
Set VHDL assert condition initial state if fed by FF
#4654
mmicko
closed
1 month ago
0
Verilog globals appended to modules instead of prepended
#4653
jmi2k
opened
1 month ago
4
dfflibmap: support flops with enable
#4652
Ravenslofty
opened
1 month ago
1
FSM pass equivalence bug
#4651
joonho3020
opened
1 month ago
3
Tribuf propagate
#4650
Rodrigodd
closed
1 month ago
1
synth_xilinx: add -json
#4649
widlarizer
closed
1 month ago
0
`sta` command hangs on some designs
#4648
lukbau
opened
1 month ago
0
CI: force brew formula update
#4647
mmicko
closed
1 month ago
0
cxxrtl: fix formatting of UNICHAR
#4646
rroohhh
closed
1 month ago
0
write_btor: only initialize array with const value when it is fully def
#4645
georgerennie
closed
1 week ago
0
code generated by `write_cxxrtl` fails to compile with big arguments to `$write`
#4644
rroohhh
closed
1 month ago
1
wheels: fix missing yosys-abc/share directory
#4643
donn
closed
1 month ago
0
Fix CI by adding lld as brew package
#4642
mmicko
closed
1 month ago
0
write_btor: don't emit undriven bits multiple times
#4641
georgerennie
closed
1 week ago
1
write_btor: Part selects of undriven signals are lowered as separate inputs
#4640
georgerennie
closed
1 week ago
0
Explictly #include <variant> for std::variant usage.
#4639
mikesinouye
closed
1 month ago
0
Co-simulation fails for $fa cell
#4638
RCoeurjoly
opened
1 month ago
7
bufnorm: avoid warning. NFC
#4637
widlarizer
closed
1 month ago
0
`tee -q -o <bad-path>` fails silently
#4636
povik
opened
1 month ago
0
Remove make docs race conditions (and other docs fixes)
#4635
KrystalDelusion
closed
1 month ago
0
make synth stuck at synth -top $::env(DESIGN_NAME) -run fine: {*}$synth_args
#4634
janboeye
closed
1 month ago
4
docs: avoid concurrency issues when generating images in parallel
#4632
tarikgraba
closed
1 month ago
1
docs images: Race between latex pdf build and "tidy"
#4631
DanielG
closed
1 month ago
1
Mapping to flip-flops with an enable in dfflibmap
#4630
povik
closed
1 month ago
3
tests: remove -seq 1 from sat with -tempinduct where possible
#4629
georgerennie
opened
1 month ago
0
Bump abc submodule
#4628
povik
closed
1 month ago
3
Assume x values for missing signal data in FST
#4627
RCoeurjoly
closed
2 weeks ago
0
select: Add new `t:@<name>` syntax
#4626
povik
closed
1 month ago
2
cellmatch: Size the `lut` attribute
#4625
povik
closed
1 month ago
0
cxxrtl: test stream operator
#4624
widlarizer
closed
1 month ago
2
log_deprecated
#4623
widlarizer
opened
1 month ago
0
abc segfaults in certain usecase
#4622
MrHighVoltage
opened
1 month ago
2
Add "Get vcd2fst" step to test-yosys job
#4621
RCoeurjoly
closed
1 month ago
0
Fix: handle VCD variable references with and without whitespace
#4620
RCoeurjoly
closed
2 weeks ago
1
Allow whitespace in `tee` command paths
#4619
malmeloo
opened
1 month ago
1
Synthesis fails on MacOS but succeeds on Linux (possibly ABC error)
#4618
agrif
opened
1 month ago
2
VCD file parsing error in sim pass with GHDL-generated VCDs due to whitespace handling
#4617
RCoeurjoly
closed
2 weeks ago
0
driver: replace getopt with cxxopts, replace -B, clean up help
#4616
widlarizer
closed
1 month ago
3
Efficient handling of patterns emitted by sv2v
#4615
povik
opened
1 month ago
7
opt_reduce: keep at least one input to $reduce_or/and cells
#4614
georgerennie
closed
2 days ago
0
log: Never silence `log_cmd_error`
#4613
povik
closed
1 month ago
1
opt_demorgan: skip zero width cells
#4612
georgerennie
closed
2 days ago
2
Yosys Synthesis Fails with std::out_of_range Error in OPT_DEMORGAN Pass
#4610
PerryLogic
closed
2 days ago
5
smtbmc: escape path identifiers
#4609
georgerennie
closed
1 month ago
0
rtlil: add Const::compress helper function
#4608
phsauter
closed
1 month ago
6
quicklogic: Avoid carry chains in division mapping
#4607
povik
closed
1 month ago
3
Nanoxplore synthesis does not works when using abc9 flow
#4606
samhanic
opened
2 months ago
1
read_liberty: Optionally import unit delay arcs
#4605
povik
closed
1 month ago
0
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