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YosysHQ
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yosys
Yosys Open SYnthesis Suite
https://yosyshq.net/yosys/
ISC License
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opt: no "-purge" option but public names removed
#4357
YikeZhou
opened
2 months ago
2
Add template for documentation issues
#4356
KrystalDelusion
closed
1 month ago
2
Should -nomx8 be the default for the GateMate?
#4355
spth
opened
2 months ago
0
Manual title page should have yosys version number
#4354
spth
closed
1 month ago
0
Crash in yosys-abc
#4352
maliberty
opened
2 months ago
0
Bump abc
#4351
povik
closed
2 months ago
2
rtlil: Add packed `extract` implementation for `SigSpec`
#4350
jix
closed
2 months ago
4
"ERROR: Assert `count_id(wire->name) == 0' failed in kernel/rtlil.cc:2143" when using synth_{ice40,ecp5} on simple design
#4349
cr1901
opened
2 months ago
3
synth_* passes should call `check -mapped`
#4348
nakengelhardt
opened
2 months ago
0
Another out-of-memory problem with for loop
#4345
YikeZhou
opened
2 months ago
0
cost: add keep_hierarchy pass with max_cost argument
#4344
widlarizer
opened
2 months ago
10
ABC: read_lib args and placeholders
#4343
phsauter
opened
2 months ago
0
Add new verific testing environment CI
#4341
mmicko
closed
2 months ago
0
add support for using ABCs library merging when providing multiple liberty files
#4340
gadfort
closed
2 months ago
6
verific: expose library name as module attribute
#4339
mmicko
closed
2 months ago
0
formalff -setundef: Fix handling for has_srst FFs
#4338
jix
closed
2 months ago
0
Yosys Fails to Synthesize Tri-State Logic Correctly for inout Ports
#4337
1353369570
closed
2 months ago
1
Inconsistency in Verilog Synthesis: Yosys Successfully Synthesizes Code That Fails in Vivado and Quartus Due to Syntax Errors
#4336
1353369570
closed
2 months ago
3
Assertion Failure in AST Processing: node->bits == v at frontends/ast/ast.cc:855
#4335
1353369570
opened
2 months ago
0
Strip compilation date from doc outputs
#4334
KrystalDelusion
closed
2 months ago
1
fix hierarchy -generate mode handling of cells
#4333
nakengelhardt
closed
2 months ago
0
Add docs generation from cells help output
#4332
KrystalDelusion
opened
2 months ago
0
Add workflows and CODEOWNERS and fixed gitignore
#4329
mmicko
closed
2 months ago
0
drivertools: Utility code for indexing and traversing signal drivers
#4328
jix
opened
2 months ago
1
techmap: Support mapping to dynamic cell types
#4327
povik
closed
2 months ago
2
Extend `log` command with `-push`, `-pop`, `-header` options
#4326
povik
closed
1 month ago
0
Latch inferred for x signal
#4325
spth
opened
2 months ago
4
Reduce default severity of Verific messages that produce warnings on commonly used coding styles
#4324
nakengelhardt
opened
2 months ago
0
Tests update for latest more strict iverilog
#4323
mmicko
closed
2 months ago
0
read_verilog: Add missing defaults for flags
#4321
KrystalDelusion
closed
1 month ago
0
write_btor: Include `$assert` and `$assume` cells in -ywmap output
#4320
KrystalDelusion
opened
2 months ago
0
fix ast ternary string extension
#4319
Khrig
opened
2 months ago
1
Parameters in other packages
#4318
pentin-as
opened
3 months ago
2
docs: Document $macc
#4316
widlarizer
closed
2 months ago
5
Proof engine is going into wrong case in case statement
#4317
lejar
closed
2 months ago
3
write_verilog: don't `assign` to a `reg`
#4314
whitequark
closed
3 months ago
0
opt_demorgan: fix extra args warning
#4313
widlarizer
closed
2 months ago
0
kernel: Avoid including files outside include guards
#4312
jix
closed
2 months ago
0
cleanup: extra_args and argidx
#4311
widlarizer
opened
3 months ago
4
write_verilog: only warn on processes with sync rules
#4310
whitequark
closed
3 months ago
0
docs: Update linux kernel coding style link
#4309
widlarizer
closed
3 months ago
0
yosys fails with 'ERROR: init_share_dirname: unable to determine share/ directory!' on macos
#4308
conversy
closed
3 months ago
3
Assertion Failure in genrtlil.cc When Handling Signedness Issue Description:
#4307
1353369570
opened
3 months ago
1
Yosys Fails to Detect Syntax Violations According to Verilog Standards
#4306
1353369570
opened
3 months ago
2
cxxrtl: Fix sdivmod
#4305
merryhime
closed
3 months ago
0
extract: add arbitrary port width matching
#4304
phsauter
opened
3 months ago
0
Infrastructure to run a Sat solver as a command
#4303
Coloquinte
opened
3 months ago
0
Verific support for VHDL 2019
#4302
mmicko
closed
2 months ago
0
Add several new formatting features used by Amaranth to translate Python format strings
#4301
whitequark
closed
3 months ago
4
cellmatch: New pass for picking out standard cells automatically
#4300
povik
closed
1 month ago
7
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