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cornell-brg
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pymtl
Python-based hardware modeling framework
BSD 3-Clause "New" or "Revised" License
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Type inference from signal lists translate into temporaries with incorrect bitwidth
#136
dmlockhart
closed
9 years ago
0
Imported VerilogModel wrappers won't dump *.verilator.vcd when vcd_file is set
#135
dmlockhart
opened
9 years ago
0
Updated processor FL and CL model
#134
cbatten
closed
9 years ago
0
Verilog translated models fail if using a BitStruct defined in a non-global scope
#133
dmlockhart
opened
9 years ago
0
Models using BitStructs don't return BitStruct objects when translated to Verilog
#132
dmlockhart
closed
9 years ago
0
[pclib] make random num gen reproducible
#131
cbatten
closed
9 years ago
0
Various checker enhancements, better Error messages
#130
dmlockhart
opened
9 years ago
0
`TranslationTool` incorrectly uses `wire` instead of `reg` for `BitStructs`
#129
cbatten
closed
9 years ago
0
SimulatorTool detects sensitivity list incorrectly for Bits in @combinational blocks
#128
dmlockhart
closed
9 years ago
0
Add checking to detect multiple identical assignments/multiple assignments to the same signal.
#127
dmlockhart
opened
9 years ago
0
Support `s.connect()` with constant `Bits` object
#126
cbatten
opened
9 years ago
0
PortBundles cannot contain lists
#125
dmlockhart
opened
9 years ago
0
Figure out a way to have a translatable truncate() function
#124
dmlockhart
opened
9 years ago
1
Throw useful Error during translation when non-literal Bits constructors encountered.
#123
dmlockhart
closed
9 years ago
0
Translation tool error: zext cannot take an element of WireList
#122
moyang
opened
9 years ago
0
Add check during simulator construction for assigning to .value in @tick or .next in @combinational
#121
dmlockhart
opened
9 years ago
0
Remove verbose and confusing sensitivity list warnings.
#120
dmlockhart
closed
9 years ago
0
Verilator model cache does not recompile if VCD dumping is enabled/disabled
#119
dmlockhart
closed
9 years ago
0
Connect error message does not report which line in model caused error
#118
cbatten
closed
9 years ago
2
Using reg as module name causes verilator error
#117
cbatten
closed
9 years ago
0
Add support for arithmetic right shift
#116
dmlockhart
opened
9 years ago
0
Template files ending in .py cause a SyntaxError warning during install
#115
dmlockhart
opened
9 years ago
0
Remove `v=` and `w=` from `__repr__`
#114
cbatten
closed
9 years ago
0
Hard-coded path to wrapper template files for translation
#113
cbatten
closed
9 years ago
0
Translation always uses non-blocking assignments in `tick`
#112
cbatten
opened
9 years ago
1
Need to change calls to `bin_str()` to `bin()`
#111
cbatten
closed
9 years ago
0
VERILATOR_ROOT not working for Verilator installed via stow
#110
cbatten
closed
9 years ago
0
Invalid negative initial values are allowed when constructing Bits
#109
cbatten
closed
9 years ago
0
Bit operations (and, or, xor) between a Bits and integer literal won't perform bit extension if literal is longer
#108
cbatten
opened
9 years ago
0
Provide a cleaner interface by not requiring dump_vcd to be passed to both get_verilated() and SimulatorTool
#107
dmlockhart
closed
9 years ago
1
Fix Verilator VCD to properly close generated .vcd file without an explicit call to destroy_model()
#106
dmlockhart
closed
9 years ago
1
Fix Verilator VCD output to appear on correct clock edge
#105
dmlockhart
closed
9 years ago
1
DotProductFL_test passes but redundantly issues many request unnecessarily. Fix!
#104
dmlockhart
opened
9 years ago
0
Fix Bits to match ap_int bitwidth extension behavior
#103
dmlockhart
opened
9 years ago
0
Fix mem/simple_cache/ClDirectMapped_test tests
#102
dmlockhart
opened
9 years ago
0
Use from __future__ import print_function to promote Python3 compatibility
#101
dmlockhart
closed
9 years ago
1
[example_gcd] GCD FL, CL, RTL models completed, code review needed
#100
wkopen
closed
9 years ago
2
Type inferences fails for BitStruct objects
#99
dmlockhart
opened
9 years ago
0
[example_gcd] GCD FL model created, test copied from pymtl/new_gcd/GcdUnitBL_test.py
#98
wkopen
closed
9 years ago
0
Fix DotProd*_test: FL/CL write .next, RTL writes .value! Also reuse tests.
#97
dmlockhart
opened
9 years ago
0
Get Verilator tests working on TravisCI
#96
dmlockhart
closed
9 years ago
1
Fix failing tests on Travis CI
#95
dmlockhart
closed
9 years ago
0
Dotprod
#94
GZibrat
closed
9 years ago
0
[dotprod] Items 1 and 2 Done
#93
GZibrat
closed
9 years ago
0
Temp variables named c aren't declared during Verilog translation
#92
dmlockhart
opened
10 years ago
0
Fix test harnesses to use py.test fixtures to enable Model reuse across tests
#91
dmlockhart
opened
10 years ago
1
Translation should raise informative exception when unsupported AST nodes are encountered
#90
dmlockhart
closed
9 years ago
0
Bits should support //
#89
cbatten
closed
9 years ago
0
Array reads on LHS of assignment translate incorrectly
#88
dmlockhart
closed
9 years ago
0
Bits multiplication behavior requires verbose PyMTL code
#87
dmlockhart
opened
10 years ago
0
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