cornell-brg pymtl issues

cornell-brg / pymtl

Python-based hardware modeling framework

BSD 3-Clause "New" or "Revised" License

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issues

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Member and temporary variables with same name cause problems in verilog translation

#86 dmlockhart opened 10 years ago
0
Bits objects instantiated within logic blocks cannot be translated by SimJIT-CL

#85 dmlockhart opened 10 years ago
0
Bits cannot not be provided as an option to Bits constructor

#84 dmlockhart closed 10 years ago
0
Bits objects cannot be used inside of ranged slices

#83 dmlockhart closed 10 years ago
1
PortLists where some ports are assigned in a concurrent block and some are structurally connected fails translation

#82 dmlockhart opened 10 years ago
0
Accessing Submodule PortList in Concurrent Block translates incorrectly

#81 dmlockhart closed 10 years ago
0
open slices (e.g., x[ :5], x[1: ], x[ : ]) are not translatable

#80 dmlockhart closed 9 years ago
1
intermittent bug involving wires connected to sliced bitstructs

#79 dmlockhart closed 9 years ago
0
Temporaries in @posedge_clk blocks don't have the semantics in Verilog and Python!

#78 dmlockhart opened 10 years ago
4
ParcProc5stBypass/ParcProc5stStall hangs when executing vvadd ubmark

#77 dmlockhart opened 10 years ago
0
ubmark build system generates incorrect benchmark code

#76 dmlockhart opened 10 years ago
2
Accessing PortBundles of Submodule List in Concurrent Block translates incorrectly

#75 dmlockhart opened 10 years ago
0
Accessing Submodule List of PortBundles in Concurrent Block translates incorrectly

#74 dmlockhart closed 10 years ago
0
Type inference fails for Bits objects

#73 dmlockhart closed 10 years ago
0
Variable Part-Selects do not translate correctly

#72 dmlockhart closed 10 years ago
0
Enable verilator VCD tracing only if --dump-vcd is provided at the command line

#71 dmlockhart closed 9 years ago
0
py.test ../new_proc/ParcProc5stStall_test.py --test-verilog fails several vmh tests

#70 dmlockhart opened 10 years ago
0
Several processor vmh tests are failing

#69 dmlockhart closed 10 years ago
2
sltu unit tests fail for ParcProc5stStall and ParcProc5stBypass

#68 dmlockhart closed 10 years ago
0
SubModule PortBundles accessed in a behavioral block translate incorrectly

#67 dmlockhart closed 10 years ago
0
Accessing Bits attributes in behavioral blocks raise AttributeError in SimulationTool

#66 dmlockhart opened 10 years ago
0
Bits instantiations within behavioral blocks cannot be translated

#65 dmlockhart closed 10 years ago
0
[vvadd] example of using greenlets for BL models

#64 cbatten closed 9 years ago
0
Slice constants used in a concurrent block are not translatable

#63 dmlockhart closed 10 years ago
0
Exception() is not translatable

#62 dmlockhart closed 10 years ago
2
BitStructs break jit-v caching

#61 dmlockhart closed 10 years ago
0
List of Wires in Concurrent Block translate incorrectly

#60 dmlockhart closed 10 years ago
0
Bitslicing List-of-Modules Ports in a Concurrent Block not translatable

#59 dmlockhart closed 10 years ago
0
Reading/Writing List-of-Modules Ports in a Concurrent Block not translatable

#58 dmlockhart closed 10 years ago
0
List of PortBundles not translatable

#57 dmlockhart closed 10 years ago
0
Nested For Loops do not translate

#56 dmlockhart closed 10 years ago
0
PortBundles cannot contain PortBundles

#55 dmlockhart opened 10 years ago
0
PortBundles cannot contain lists of Ports

#54 dmlockhart closed 10 years ago
1
Catch invalid params for @s.tick/@s.posedge_clk/@s.combinational blocks

#53 dmlockhart opened 10 years ago
0
C Translation cannot translate Object message types

#52 dmlockhart opened 10 years ago
0
C Translation cannot translate Bits

#51 dmlockhart opened 10 years ago
0
Shared libraries created during cpp translation should start with 'lib'

#50 dmlockhart opened 10 years ago
0
Fix manual cpp harnesses in no_python to match updated generated cpp code

#49 dmlockhart closed 10 years ago
0
C Translation Python harnesses exposes PortBundles as separate wires

#48 dmlockhart closed 10 years ago
1
C Translation Python harnesses don't use .value/.next

#47 dmlockhart closed 10 years ago
1
connecting a model OutPort to a submodel InPort using slices does not simulate correctly

#46 dmlockhart closed 10 years ago
0
executing 'py.test --test-verilog' with pypy results in libffi segfaults

#45 dmlockhart opened 10 years ago
0
Cannot infer temporary bitwidth when a previously inferred temporary on RHS

#44 dmlockhart closed 9 years ago
1
Synopsys DesignCompiler requires inputs/outputs to have reg/wire labels

#43 dmlockhart closed 10 years ago
0
Verilog signals used before reg declaration fail on VCS due to one pass compilation

#42 dmlockhart closed 10 years ago
0
Add py.test check to skip tests dependent on iverilog if it is not installed

#41 dmlockhart closed 10 years ago
0
Provide a way to generate Verilog ready to use Synopsys DesignWare components

#40 dmlockhart opened 10 years ago
0
variables containing Bits are not converted into verilog params

#39 dmlockhart closed 10 years ago
0
verilog translation should generate localparam rather than param for constants scoped within a module

#38 dmlockhart closed 10 years ago
0
multiple assignments to a temporary result in 'duplicate declaration' errors in verilog

#37 dmlockhart closed 10 years ago
0

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