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enjoy-digital
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litedram
Small footprint and configurable DRAM core
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is IRC of litex not active?
#259
ombhilare999
closed
3 years ago
1
DFI rate converter
#258
jedrzejboczar
closed
2 years ago
3
LPDDR4 code refactor
#257
jedrzejboczar
closed
3 years ago
1
Leveling fails for DFI databits < 32
#256
jedrzejboczar
closed
2 years ago
1
Fix test_lpddr4.VerilatorLPDDR4Tests.test_lpddr4_sim_x2rate_no_cache.
#255
enjoy-digital
closed
3 years ago
4
Generation with AXI interface
#254
lindajames101
closed
3 years ago
1
fix gcc warning: function used but not defined
#253
gsomlo
closed
3 years ago
3
init: generate sdram_phy.h in a way that allows to include it in multiple units
#252
jedrzejboczar
closed
3 years ago
1
Why is my simulation different to my target in regard to "address endianness"?
#251
nickoe
opened
3 years ago
1
Only update UpConverter sel when input valid
#250
andrewb1999
closed
3 years ago
1
Fix adapter reverse typo
#249
andrewb1999
closed
3 years ago
0
init/lpddr4: make some settings configurable via phy_settings
#248
jedrzejboczar
closed
3 years ago
1
Fix UpConverter reversed write mask
#247
andrewb1999
closed
3 years ago
1
Race condition when prematurely aborting Wishbone transactions
#246
jfng
closed
3 years ago
6
add support for Winbond W9825G6KH-6 at 50MHz 1:2 rate
#245
hansfbaier
closed
2 years ago
2
Add DQ-DQS training for LPDDR4 PHY
#244
jedrzejboczar
closed
3 years ago
1
Generating a PHY only design
#243
fatihgulakar
closed
3 years ago
1
lpddr4: add missing copyright comments
#242
jedrzejboczar
closed
3 years ago
1
Fix Python header generation for LPDDR4
#241
jedrzejboczar
closed
3 years ago
1
lpddr4: add a local README with a summary of the code
#240
jedrzejboczar
closed
3 years ago
1
LPDDR4 / Add optional features support
#239
jedrzejboczar
opened
3 years ago
0
core/refresher: use A10=1 for an all-banks REF
#238
jedrzejboczar
closed
3 years ago
0
core: use wider DFI address/bank if PHY requires it
#237
jedrzejboczar
closed
3 years ago
0
modules.py: Add MT41J256M8 (Passes mem_test on HW @ sys4x=500MHz, vex…
#236
jersey99
closed
3 years ago
1
simple example to read-write for the standalone core?
#235
particlerain
closed
3 years ago
4
Add module name CLI option
#234
craigjb
closed
3 years ago
0
Add support for DDR3 in MAX10
#233
rdolbeau
opened
3 years ago
5
init: make the write leveling MR bit configurable
#232
jedrzejboczar
closed
3 years ago
1
Allow to pass all module timings in the format (ck, ns)
#231
jedrzejboczar
closed
3 years ago
1
test: improve error messages when comparing files in test_init.py
#230
jedrzejboczar
closed
3 years ago
1
Add customizable standalone user port data widths
#229
craigjb
closed
3 years ago
2
modules: add IS43TR16256A support.
#228
garytwong
closed
3 years ago
0
phy/ecp5ddrphy: invert the clock signal if necessary.
#227
garytwong
closed
3 years ago
4
modules: add MT48LC32M8 SDR module
#226
mdpye
closed
3 years ago
1
Wrong DQS pattern preamble/postamble
#225
jedrzejboczar
opened
3 years ago
2
Add LPDDR4 PHY
#224
jedrzejboczar
closed
3 years ago
7
ecp5ddrphy: Fix DELAYF initial value
#223
gregdavill
closed
3 years ago
1
init: Cast DDR4 RCD fine_speed to int
#222
daveshah1
closed
3 years ago
1
Add dynamic write latency calibration.
#221
enjoy-digital
closed
3 years ago
3
Native Interface Documentation and Simulation
#220
vasimr
opened
3 years ago
2
Core Question
#219
vasimr
opened
3 years ago
4
Update .travis.yml
#218
pragyabansal02
closed
3 years ago
1
Update .travis.yml
#217
pragyabansal02
closed
3 years ago
1
Check default DDR3 termination settings/power consumption on ECP5/OrangeCrab
#216
enjoy-digital
closed
3 years ago
4
Support for DRAM on Lattice ICE40HX devices?
#215
adamfeuer
closed
3 years ago
3
Feedback / Contribution / Support
#214
enjoy-digital
opened
3 years ago
0
Arty A7 LiteX SoC memory test runs extremely slowly
#213
alanvgreen
closed
3 years ago
5
Check DM polarity on DDR4
#212
enjoy-digital
closed
3 years ago
4
Add support for Etron RPC DRAM
#211
jedrzejboczar
opened
3 years ago
7
Add support for TDQS mode.
#210
oskirby
closed
3 years ago
1
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