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enjoy-digital
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litedram
Small footprint and configurable DRAM core
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Simulation issue, Arty S7 (Beginner)
#309
TheAnimatrix
closed
1 year ago
9
QuarterRateGENSDRPHY
#308
machdyne
opened
2 years ago
2
New to LiteDRAM
#307
FATHY174
closed
2 years ago
2
Why are CL and CWL not included as speedgrade parameters in the module class?
#306
jaccharrison
opened
2 years ago
1
DDR4 Memtest Failed
#305
zhbeiluo
closed
2 years ago
3
Strategy steering: Best way to stream data into a custom accelerator when litedram is being used inside Litex SoC?
#304
francis2tm
closed
2 years ago
4
LiteDRAM USPDDRPHY unable to meet DDR4 timing requirements?
#303
jaccharrison
opened
2 years ago
8
dfi: add possibility to have an external dfi injector
#302
acomodi
closed
2 years ago
0
Added AS4C4M16 for Arduino MKR Vidor 4000 support
#301
Johnsel
closed
2 years ago
0
Allow for variable DQ/DQS ratio
#300
RRozak
closed
2 years ago
3
ULX4M DM signal is not connected to DQS group
#299
goran-mahovlic
closed
2 years ago
2
Help creating verilog module to go from Wishbone4 to Litedram native port
#298
fontamsoc
closed
2 years ago
1
Unable to run Litedram on Digilent Genesys2
#297
fontamsoc
closed
2 years ago
6
memtest fails on arty depending on read leveling outcome
#296
acomodi
closed
2 years ago
3
s7phy: fix DDR4 mode
#295
acomodi
closed
2 years ago
2
phy/s7ddrphy: Write latency calibration always.
#294
kaolpr
closed
2 years ago
1
Initialization failed on Artix after e5e3b6c
#293
kaolpr
closed
2 years ago
5
litedram_gen: Don't block user port with no CPU
#292
mkj
closed
2 years ago
1
LDDR5 Support
#291
pjattke
closed
2 years ago
2
add support for MT41K256M8 module
#290
tongchen126
closed
2 years ago
1
generate user interface
#289
12ff7a6
closed
2 years ago
1
Possible to Create Software Initialization File Without Regenerating Core?
#288
jacquuelinee-b
closed
2 years ago
1
add LPDDR module
#287
cklarhorst
closed
2 years ago
1
litedram_gen fixes for ECP5
#286
mkj
closed
2 years ago
1
DDR3 Memory on Kintex7 325T based board randomly fails
#285
tongchen126
closed
2 years ago
48
W9825G6KH6 seems to use 8192 refresh cycles not 8000
#284
hansfbaier
closed
2 years ago
1
modules: add other RDIMM modules
#283
acomodi
closed
2 years ago
1
frontend/fifo.py: The fifo_depth was being set incorrectly.
#282
jersey99
closed
2 years ago
4
Help generating DDR3 Verilog module for Digilent NexysVideo Artix-7 FPGA
#281
tambewilliam
opened
2 years ago
3
Fix a few issues with ECP5 standalone generator
#280
antonblanchard
closed
2 years ago
4
Upconverter rewrite
#279
mtdudek
opened
2 years ago
4
Fix generation with no CPU
#278
ozbenh
closed
2 years ago
2
phy: s7: add DDR4 memtype as well
#277
acomodi
closed
2 years ago
3
litedram_gen: Fix duplicate with_uart value when cpu_type is None.
#276
jfng
closed
2 years ago
1
modules: add more RDIMM modules
#275
acomodi
closed
2 years ago
3
Add AS4C128M16 DDR3L-1600 ram
#274
teknoman117
closed
2 years ago
1
Add RPC DRAM support
#273
jedrzejboczar
closed
2 years ago
1
The MAX sys_clk_freq supported of DDR4
#272
uxilinx
closed
2 years ago
1
litedram_gen: Fix error with --sim option
#271
antonblanchard
closed
2 years ago
1
LPDDR5 support
#270
jedrzejboczar
closed
2 years ago
2
DFI rate converter - 2nd attempt
#269
jedrzejboczar
closed
2 years ago
1
Refactor init code generation
#268
jedrzejboczar
closed
2 years ago
2
LPDDR4 minor refactor
#267
jedrzejboczar
closed
2 years ago
1
gen: use sys_clk_freq for SDRAMPHYModel timings, instead of 100MHz.
#266
jfng
closed
2 years ago
4
Figure out how to hook LiteDRAM to the WDDR PHY
#265
mithro
opened
2 years ago
1
Changes to tREFI ignored
#264
SLongofono
closed
2 years ago
5
litedram does not use full address space?
#263
Aljeshka
closed
2 years ago
7
sdram.c:39:37: error: static declaration of 'cdelay' follows non-static declaration
#262
hansfbaier
closed
2 years ago
1
SDRAMPHYModel should pick sane default PHY settings
#261
thirtythreeforty
closed
2 years ago
6
SDRAM support for standalone core
#260
ombhilare999
closed
3 years ago
3
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