issues
search
enjoy-digital
/
litedram
Small footprint and configurable DRAM core
Other
383
stars
122
forks
source link
issues
Newest
Newest
Most commented
Recently updated
Oldest
Least commented
Least recently updated
frontend/dma.py: Remove left-over rsv_level documentation
#361
david-sawatzke
opened
3 weeks ago
0
litedram/address_mapping Add bank_byte_alignment
#360
Dolu1990
closed
3 months ago
1
modules: add Insignis NDS36PT5
#359
maass-hamburg
closed
5 months ago
1
Wishbone, 2 writes followed by colliding read returns incorrect result, write stuck in FIFO
#358
epsilon537
opened
6 months ago
2
Adding support to gowin phys in litedram.gen?
#357
linhz0hz
opened
7 months ago
1
LiteDRAMDMAWriter sinks data when not enabled
#356
DaveBerkeley
opened
7 months ago
2
Wishbone port does not accept more than one operation despite cmd_buffer_depth non-null in LiteDram yaml file,
#355
fontamsoc
opened
8 months ago
0
stable avalon frontend
#354
hansfbaier
closed
8 months ago
1
GENDDRPHY support?
#353
rhgndf
opened
10 months ago
0
litedram/phy/lpddr*: fix use of invalid escape sequence
#352
maribu
closed
8 months ago
1
phy/gw5ddrphy: introducing GW5A DDR phy
#351
trabucayre
closed
1 year ago
1
Add W9812G6JB SDRAM module
#350
hansfbaier
closed
1 year ago
1
litedram with vexriscv DDR4 SODIMM fails memtest (Xilinx VU9P + spd)
#349
jersey99
opened
1 year ago
5
Use bump2version to keep code and tag in sync, small cleanups and enhancements
#348
timkpaine
opened
1 year ago
0
DE10-Lite Memory initialization failed
#347
LearnShareAlways
opened
1 year ago
0
Underclocking DRAM controler to increase access time
#346
denishoornaert
opened
1 year ago
0
LiteDRAM core targeting DDR3 issues activate command twice for a write operation
#345
dinaabdelbaky
opened
1 year ago
0
LiteDRAM DDR3 Core targeting Arty AXI read data appears on the Native port instead.
#344
dinaabdelbaky
opened
1 year ago
1
phy/gw2ddrphy: migen.genlib -> litex.gen.genlib (fix commit 6297370e3c)
#343
trabucayre
closed
1 year ago
1
Axi port write data error
#342
Yuxin-Yu
opened
1 year ago
8
add burst converter tests, fix downconverting burst
#341
hansfbaier
closed
1 year ago
3
frontend/avalon: properly implement bursts
#340
hansfbaier
closed
1 year ago
35
Is it possible to adjust burst-length in order to widen data path ?
#339
fontamsoc
opened
1 year ago
0
wb_ctrl ports of ECP5 litedram_core generated for OrangeCrab02-25F failing when user_ports is native
#338
fontamsoc
opened
1 year ago
0
Avalon frontend for LiteDRAM
#337
hansfbaier
closed
1 year ago
11
LiteDRAMDMAWriter cannot write accurate data to a specific address?
#336
Prigana
opened
1 year ago
0
Fix AxSIZE
#335
TheZoq2
opened
1 year ago
0
AxSIZE mismatch?
#334
TheZoq2
opened
1 year ago
1
Setting for user_clk
#333
ztachip
opened
1 year ago
1
Add support for clam shell topology
#332
jiegec
closed
1 year ago
1
Generate liteDRAM verilog file
#331
ztachip
closed
1 year ago
4
add manifest, uplift setup.py to pass twine checks
#330
timkpaine
closed
1 year ago
1
ulx3s example does not work
#329
TheZoq2
opened
1 year ago
3
DDR4 reads without DQS at high speeds?
#328
alexey-morozov
opened
1 year ago
1
Carrying out the LiteDRAM standalone core initialization manually, through wishbone ctrl interface
#327
dinaabdelbaky
opened
1 year ago
5
phy/gw2ddrphy: supressing warnings about unconnected and bit length.
#326
trabucayre
closed
1 year ago
1
--top-module 'sim' was not found in the design
#325
CarrolXC
opened
1 year ago
5
Need Help Generating Verilog DRAM controller, while maininting module hiraerachies.
#324
dinaabdelbaky
closed
1 year ago
1
Mczyz/ddr5 rcd01
#323
mczyz-antmicro
closed
1 year ago
0
Make tests safe to run in parallel
#322
michalsieron
closed
1 year ago
1
frontend/bist: replicate LFSR output to fill the DRAM port
#321
michalsieron
closed
1 year ago
7
init: Define `SDRAM_PHY_[DDR3|DDR4|...]` and `SDRAM_PHY_SUPPORTED_MEMORY`
#320
michalsieron
closed
1 year ago
2
frontend/bist: properly signal finished writes
#319
michalsieron
closed
1 year ago
1
DMA AXI BUG
#318
mohammadshahidzade
closed
1 year ago
1
Corresponding verilog testbench for ASIC
#317
CarrolXC
opened
1 year ago
1
submodules verilog
#316
CarrolXC
opened
1 year ago
2
sdram_init() vs. init_sequence()
#315
epsilon537
opened
1 year ago
0
Fix DFITimingsChecker for DDR4 simulation
#314
michalsieron
closed
2 years ago
1
Add MT46H128M16 and change bankmaschine to not use A10 for col addresses.
#313
cklarhorst
closed
1 year ago
1
Typical litedram-L2 port sizes
#312
bala122
opened
2 years ago
0
Next