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gaph-pucrs
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RS5
RV32I[M][C][V][_Zihpm][_Zkne][_Xosvm]_Zicsr processor
MIT License
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Missing script for Toolchain installation
#33
mvaranda
opened
3 days ago
1
No Issue (just a question in Portuguese)
#32
mvaranda
opened
3 days ago
2
Register instruction in fetch stage before using in decoder
#31
aedalzotto
opened
1 week ago
0
Add vector profiling
#30
santosantonio1
opened
1 week ago
0
FIx logic synthesis warnings
#29
cominixo
closed
2 weeks ago
0
fixes reset else condition
#28
LucasDamo22
closed
1 month ago
0
Plic spec && align fix
#27
LucasDamo22
closed
1 month ago
0
Logic synth rs5
#26
dubernardon
closed
2 months ago
2
Vector extension merge
#25
Willian-Nunes
closed
3 months ago
0
Proto improvement and AES timing fix
#24
aedalzotto
closed
3 months ago
0
changed 'auto' ack from plic to periph, to a specific write addr
#23
LucasDamo22
closed
4 months ago
0
implemented sw_rst
#22
vitorbzanini
closed
4 months ago
0
Add C (compressed) extension
#21
cominixo
closed
4 months ago
4
Add support for Zkne extension
#20
cggewehr
closed
5 months ago
0
Make resets active low and asynchronous
#19
cominixo
closed
5 months ago
0
Re-add Verilator compatibility, fix some bugs and update tests
#18
aedalzotto
closed
6 months ago
1
Add a multiplication module for ASIC/FPGA
#17
LucasDamo22
closed
6 months ago
0
Add UART RX peripheral
#16
LucasDamo22
closed
6 months ago
0
Parameterization
#15
Willian-Nunes
closed
11 months ago
0
PLIC + OS Support
#14
aedalzotto
closed
1 year ago
0
Plic
#13
Willian-Nunes
closed
1 year ago
0
Multiply Extension
#12
Willian-Nunes
closed
1 year ago
1
Core rename
#11
Willian-Nunes
closed
1 year ago
0
Memory Writes are performed in third stage
#10
Willian-Nunes
closed
1 year ago
4
Alu
#9
Willian-Nunes
closed
1 year ago
0
Add a simple MMU
#8
carol045
closed
1 year ago
4
Branch Prediction
#7
Willian-Nunes
closed
1 year ago
0
Refactor decoding
#6
aedalzotto
closed
1 year ago
5
Branch prediction
#5
Willian-Nunes
closed
1 year ago
2
2 stage forwarding
#4
Willian-Nunes
closed
1 year ago
1
Adicionar RTC conforme especificação do RISC-V
#3
carol045
closed
1 year ago
2
Loop infinito vazio impede interrupções
#2
carol045
closed
1 year ago
0
Simulação com o Verilator
#1
aedalzotto
closed
1 year ago
2