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Hello,
We are exploring if Moore can be used to generate AST for the System Verilog Test Bench code as well. Is there a plan to support AST generation for Classes/Constraints/Interfaces?
Regards
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**Which problem is this feature request solving?**
Instance, net, and reg in the VSCode outline use the same icons, making them difficult to distinguish.
This forces me to look at the small prin…
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I believe it could be interesting to add the verification academy forum to the dataset.
- This forum focus on System Verilog and UVM languages and some verilog.
The forum is very well structured a…
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### Version
Yosys 0.33+6 (git sha1 41b34a193, clang 16.0.0 -fPIC -Os)
### On which OS did this happen?
Linux
### Reproduction Steps
```
interface testinterface();
logic [7:0] A;…
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I'm trying to use this code in a Spartan 6 board, however ISE14.7 does not support System Verilog.
Vivado supports SV but not Spartan 6 family :-(
I tried to translate this code to Verilog but packe…
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Icarus Verilog does not support the System Verilog used in the [fx68k](https://github.com/ijor/fx68k) M68000 open source core.
It seems like these two features are missing:
1. Support top level …
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VPR can write post synthesis netlist (it is more of a post-pnr netlist IMO) as BLIF and Verilog. In the BLIF file unconnected input and output ports are tied to special nets named `__vpr__unconnXX` wh…
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Jared added support for parsing System Verilog Assertions (SVAs) in VL. It'd be nice if these SVAs could have meaningful semantics in SV. Furthermore, it'd be good SVAs could be transformed into Ver…
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```
What steps will reproduce the problem?
1. ./odin_II.exe -V top_UART.v -a sample_arch.xml
2. Run in Icarus Verilog and the verilog file compiles and runs
3.
What is the expected output? What do yo…
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```
What steps will reproduce the problem?
1. ./odin_II.exe -V top_UART.v -a sample_arch.xml
2. Run in Icarus Verilog and the verilog file compiles and runs
3.
What is the expected output? What do yo…