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lowRISC
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lowrisc-chip
The root repo for lowRISC project and FPGA demos.
http://www.lowrisc.org/
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How to change the address map of 0x0~0x0FFF)FFFF, for exmaple interrupt controller
#112
nicolast0604
opened
5 years ago
1
What is the max frequency that rocket-chip could run on xc7k325T-2?
#111
hyf6661669
closed
5 years ago
1
BRAM Size
#110
furkanturan
closed
5 years ago
2
Boot procedure bare-metal
#109
bnkla
closed
5 years ago
11
Generating emulators
#108
ChafikSohaib
closed
5 years ago
4
OpenOCD and GDB debugging with Spike
#107
ChafikSohaib
closed
5 years ago
2
Nasti Lite transactions make processor hang
#106
beatsnbytes
closed
5 years ago
5
FPGA bare-metal
#105
nasahlpa
closed
5 years ago
1
(iomshr) address check to determine io has bug?
#104
beatsnbytes
closed
5 years ago
4
Simulating lowrisc chip
#103
bnkla
closed
5 years ago
3
Eth 8packets
#102
clare7
opened
5 years ago
5
kc705_mii branch status VS releases
#101
GuillemCabo
closed
5 years ago
2
L1 Cache replacement policy
#100
beatsnbytes
opened
6 years ago
7
Update README.md (docs, restructure)
#99
luismarques
closed
5 years ago
0
Traffic statistics link broken
#98
luismarques
opened
6 years ago
0
Issue building Debian for riscv-64.
#97
marthinwurer
opened
6 years ago
4
fix a wrong PA address width in tagcache
#96
wsong83
closed
6 years ago
4
boot procedure for kc705_mii branch
#95
GuillemCabo
closed
6 years ago
3
Does refresh-v0.6 support multicore on fpga?
#94
LuXuKun
closed
5 years ago
15
iomshr stores to axi-lite slave
#93
GuillemCabo
closed
6 years ago
5
Question about License
#92
sxu55
opened
6 years ago
1
Segmentation Error
#91
clare7
closed
6 years ago
6
Question about SRAM assumptions in the dcache pipeline
#90
sxu55
closed
6 years ago
4
make bitstream failed
#89
xubaqian
closed
6 years ago
15
Failure during the toolchain build
#88
noureddine-as
closed
6 years ago
2
Failed to run programs on FPGA
#87
xubaqian
closed
6 years ago
3
Defining the boot process for bare metal?
#86
sherrbc1
opened
6 years ago
5
Linux boot procedure
#85
hylee17
opened
6 years ago
3
Expand switches for MAC address selection, update boot.mem accordingl…
#84
jrrk
closed
6 years ago
0
Ethernet license conversion adaptation to Forencich
#83
jrrk
closed
6 years ago
2
Change in bus width for NastiIO
#81
clare7
opened
6 years ago
13
Can I ask you a question about the simulation?
#80
thecakim
closed
6 years ago
0
lowrisc-chip and rocket-chip
#79
chinmayaPesonal
opened
7 years ago
5
BlackBox
#78
clare7
closed
7 years ago
2
When building the rootfile system, I want to put riscv-gnu-toolchain.
#77
hylee17
opened
7 years ago
1
How long does it take to boot Linux?
#76
hylee17
closed
7 years ago
41
how to add new instruction
#75
thecakim
opened
7 years ago
1
Compile the RISC-V Linux and the ramdisk `root.bin`
#74
thecakim
opened
7 years ago
2
Update lowRISC with the upstream Rocket-chip [WIP]
#73
wsong83
closed
7 years ago
1
PPA Comparison
#72
riscveval
opened
7 years ago
4
L1 nbdcache bug?
#71
sxu55
closed
7 years ago
11
Question about release merging in the acqTracker
#70
sxu55
closed
7 years ago
2
+waitdebug problem
#69
clare7
opened
7 years ago
14
Compilation error after Enable Debug at lowRISCv0.4
#68
jawadhy
closed
7 years ago
2
Possible deadlock in multicore config?
#67
sxu55
closed
7 years ago
21
Errors : Add a DMA master device in LowRiSC
#66
sumancu
closed
7 years ago
12
Running the VCS simulator
#65
clare7
closed
7 years ago
9
Merge upstream Rocket-Chip to support Chisel3+TileLink2+Diplomacy+PLIC-Debug [WIP]
#64
wsong83
closed
7 years ago
4
add supporting VC707 board
#63
phthinh
closed
7 years ago
17
Mode of satp(or sptbr) register in lowrisc
#62
Ddnirvana
closed
7 years ago
4
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