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rachelselinar
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ReGDS-Logic-Gate-Extraction
A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog netlist, in the presence of logic gate defintions from the standard cell library.
GNU General Public License v3.0
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Regarding runtime for c499 benchmark ckt
#8
natrajbhargav
opened
1 month ago
0
Regarding Runtime working on in your github code
#7
natrajbhargav
opened
1 month ago
0
Regarding Runtime comparison with existing algorithm and proposed algorithm when both tech nodes are different?
#6
natrajbhargav
opened
1 month ago
0
Regarding more runtime in LGE algorithm
#5
natrajbhargav
closed
1 month ago
1
Regarding ReGDS paper runtime is more in your github code giving our spicenetlist input
#4
natrajbhargav
closed
1 month ago
2
Question for Parsing Error
#3
ApeachM
closed
2 years ago
1
Question about available toy examples
#2
microhumanis
closed
2 years ago
1
Can you provide some test files?
#1
huangjunying
closed
2 years ago
3