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riscv-non-isa
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riscv-iommu
RISC-V IOMMU Specification
https://jira.riscv.org/browse/RVG-55
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Incomplete check of "cause = 263" about RESERVED bits in msipte.translate_rw
#287
HDntown
closed
6 months ago
1
Fix IOVA bits 63:32 must be 0 check for SXL=1
#286
ved-rivos
closed
7 months ago
0
Question about VA fault detection in system both support Sv32 and Sv39
#285
viktoryou
closed
7 months ago
1
Sorry,how to configure the value of capabilities.PAS?
#284
augsug
closed
7 months ago
4
Fix missing fault logging in reference model for ATS Translation request with UR/CA resp…
#283
ved-rivos
closed
7 months ago
0
D-bit description is wrong in the last version of specification
#282
zetalog
closed
7 months ago
3
How does IOMMU ensure that it does not receive outdated PCIe inbound traffic after completing TLB invalidation?
#281
18772820305
closed
8 months ago
10
how to understand the PR/PW bit in IOFENCE command.
#280
runninglinuxkernel
closed
9 months ago
4
remove "PDT" word
#279
runninglinuxkernel
closed
9 months ago
4
How to invalidate the MSI page table cache?Are the two addresses A in Figure 1 and Figure 2 the same?
#278
18772820305
closed
9 months ago
5
has SIOV support for RISC-V?
#277
runninglinuxkernel
closed
9 months ago
2
Issue 275
#276
ved-rivos
closed
9 months ago
0
the reserved bit width should be 16
#275
baimengwei
closed
9 months ago
2
Question about "is_exec" & "priv" in ref model
#274
hsxyb
closed
10 months ago
3
First Stage Translation Clarification
#273
just-for-fun-too
closed
11 months ago
4
Why add these two commits? Is there any basis related to the specification, or these are implemention defined?
#272
baimengwei
closed
11 months ago
5
Fix return values
#271
ved-rivos
closed
11 months ago
0
Why this code in the line return 1 rather than -1, is this a slip?
#270
baimengwei
closed
11 months ago
1
do not qualifty is_exec for untrans with pid_valid
#269
ved-rivos
closed
11 months ago
0
How does the IO-bridge handle ATS translation requests when the address is a virtual interrupt file address?
#268
18772820305
closed
11 months ago
4
ATS Control Register Field STU and IOMMU
#267
just-for-fun-too
closed
11 months ago
2
Fix index wrap around in model
#266
ved-rivos
closed
11 months ago
0
it seems that the fault queue overflow flag in the reference model lake a condition?
#265
baimengwei
closed
8 months ago
5
do not qualify exec_req with pid_valid for untranslated requests
#264
ved-rivos
closed
11 months ago
0
Can you tell me exactly what the further records refer to?
#263
wangyongzhen0322
closed
11 months ago
4
Why the status is set to Success,when no other faults were encountered but the "Page Request" could not be queued due to the page-request queue being full (pqt == pqh - 1) or had a overflow (pqcsr.pqof == 1)?
#262
wangyongzhen0322
closed
11 months ago
4
How should IOMMU recover the faulty request?
#261
18772820305
closed
1 year ago
4
Why are the ITag fields and related errors that appear on ATS invalidation completion not mentioned in the IOMMU?
#260
wangyongzhen0322
closed
1 year ago
3
Some questions about IOMMU validation commands
#259
18772820305
closed
1 year ago
4
Errata Fixes
#258
rpsene
closed
1 year ago
0
Detect Docker robustly
#257
a4lg
closed
1 year ago
0
Some questions about the record generate in the fault queue
#256
wangyongzhen0322
closed
1 year ago
3
PDT and DDT indices should be 16-bit wide
#255
ved-rivos
closed
1 year ago
0
Can you clarify "command-queue access"
#254
hsxyb
closed
1 year ago
8
locate_device_context - overflow in uint8_t DDI[1]
#253
sometimesawake
closed
1 year ago
1
Could you please explain why it is not necessary to set V bit to 0 when doing a page size promotion or demotion?
#252
baimengwei
closed
1 year ago
2
fix pc field order
#251
ved-rivos
closed
1 year ago
0
process_context_t double-word ordering
#250
sometimesawake
closed
1 year ago
1
Is there a situation where DevATC stores SPA and the device is controlled by Guest OS?
#249
baimengwei
closed
1 year ago
2
How should the host bridge handle it abort the no corresponding field when use tr_req_ctl ?
#248
baimengwei
closed
1 year ago
1
Why reports a "Transaction type disallowed" fault when the IOVA is determined to be that of a virtual interrupt file and the corresponding MSI PTE is in MRIF mode?
#247
baimengwei
closed
1 year ago
2
Is the IOMMU serve as a part of an EP device to provide services for the device itself, or is the IOMMU serve as an EP function for other EP devices?
#246
baimengwei
closed
1 year ago
2
In which privileged state is it reasonable to execute the IOTINVAL.VMA instruction?
#245
baimengwei
closed
1 year ago
5
Why is it necessary to invalidate the page table when DC.fsc.MODE == Bare?
#244
baimengwei
closed
1 year ago
13
Clarification updates to IOMMU v1.0.0
#243
ved-rivos
closed
1 month ago
19
INVAL_DDT command seems to have no PV position, but how to specify PV=0?
#242
baimengwei
closed
1 year ago
3
bug fix - issue 240
#241
ved-rivos
closed
1 year ago
0
Question about iohpmctr in iommu_ref_model
#240
baimengwei
closed
1 year ago
2
Can a IOVA be a SPA?
#239
baimengwei
closed
1 year ago
2
Can A in the first step of MSI translation process be directly IOVA?
#238
18772820305
closed
1 year ago
6
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