sgherbst anasymod issues

sgherbst / anasymod

A framework for FPGA emulation of mixed-signal systems

BSD 3-Clause "New" or "Revised" License

33 stars 9 forks source link

issues

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Hello everyone! I’m just starting 😉

#56 bassTon05 opened 4 months ago
0
Delete unused buildkite pipeline/webhook

#55 steveri opened 5 months ago
0
Add support for using SymbiFlow open source tooling instead of Vivado

#54 mithro opened 3 years ago
1
Consider using edalize to drive EDA tooling

#53 mithro opened 3 years ago
1
Various new features

#52 sgherbst closed 3 years ago
0
Add method to auto-populate sim_ctrl.sv I/Os and initialization

#51 sgherbst opened 3 years ago
0
Add semi-custom firmware option

#50 sgherbst opened 3 years ago
0
Provide method to add user-defined synthesis/implementation constraints

#49 sgherbst opened 3 years ago
0
Provide method to get UART port / PySerial object without programming FPGA

#48 sgherbst opened 3 years ago
0
Provide method to adjust synthesis and implementation effort

#47 sgherbst opened 3 years ago
0
Update readme

#46 sgherbst closed 3 years ago
0
Add AFE example

#45 sgherbst closed 3 years ago
0
Fix cvxpy issue

#44 sgherbst closed 3 years ago
0
Provide method to treat *.v files as SystemVerilog files in Vivado

#43 sgherbst opened 3 years ago
1
Small fixes

#42 sgherbst closed 3 years ago
0
Add ZCU102 support

#41 sgherbst closed 3 years ago
0
Small updates to support a non-emulation use case

#40 sgherbst closed 3 years ago
2
Update README.md

#39 sgherbst closed 3 years ago
1
Feature/merge GitHub resolve func issue

#38 gabrielrutsch closed 3 years ago
6
Add support for ZCU106 board

#37 sgherbst closed 3 years ago
0
Use tree structure to take the minimum of timestep requests

#35 sgherbst opened 4 years ago
0
Make it harder to accidentally delete bitfiles

#34 sgherbst opened 4 years ago
0
Add more descriptive message when xsct cannot be found

#33 sgherbst opened 4 years ago
0
Add support for VCS simulator

#32 sgherbst opened 4 years ago
0
Get error_recognition test working for xrun

#31 sgherbst closed 4 years ago
0
Update README.md

#30 sgherbst opened 4 years ago
0
Merge testing setups & miscellaneous features

#29 sgherbst closed 4 years ago
0
Firmware build process does not raise an exception on build errors

#28 sgherbst closed 4 years ago
0
Synonyms for simulator names

#27 sgherbst closed 4 years ago
0
Support -unbuffered option for xrun simulator

#26 sgherbst closed 4 years ago
1
Allow user to re-run simulation while waveform remains loaded in SimVision

#25 sgherbst closed 4 years ago
0
Add support for Ultra96 board

#24 sgherbst opened 4 years ago
0
Add support for running designs from the PS clock.

#23 sgherbst opened 4 years ago
0
Add test that includes a generated gated clock

#22 sgherbst closed 4 years ago
0
Improve coverage of uart_ctrlapi.py and vio_ctrlapi.py

#21 sgherbst closed 4 years ago
0
Improve coverage of analysis.py

#20 sgherbst opened 4 years ago
0
Add regression test for EDIF support

#19 sgherbst opened 4 years ago
0
Add more extensive nightly or weekend regression test

#18 sgherbst opened 4 years ago
0
Add tests for new emulation control functions

#17 sgherbst opened 4 years ago
0
Test Xcelium simulation in regression suite

#16 sgherbst closed 4 years ago
0
Add support for ZC706 board

#15 sgherbst closed 4 years ago
1
Vitis support

#14 sgherbst closed 4 years ago
1
Add support for EDIF files and update Zynq UART support

#13 sgherbst closed 4 years ago
1
Feature/inicio dev 2354

#12 sgherbst closed 4 years ago
0
Duplicated time points in waveforms from simulation and emulation

#11 sgherbst opened 4 years ago
0
Add Windows to the list of platforms checked with the regression server

#10 sgherbst closed 3 years ago
0
Add Xcelium to list to simulators checked on regression server

#9 sgherbst closed 4 years ago
0
Consider changing the default timescale

#8 sgherbst opened 4 years ago
0
Updates to emulation control

#7 sgherbst closed 4 years ago
1
Handling of VIO analog signals + Add test of msdsl functions

#6 sgherbst closed 4 years ago
1