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I coded up a simple Verilog module and added it to a project on TerosHDL:
When I hover my mouse over the…
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When I follow the instructions from the beginning, when I get to the step of creating a mac address, I get this error. Does anyone know the solution? Please help me, thanks in advance TT
`$ make -C…
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Previously we had FPGA specific attributes in `intelfpga` namespace, so it was pretty much obvious to which device they belong. Now when `intelfpga` was deprecated in favor of just `intel` namespace w…
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```
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u155004@s005-n003:~$ tools_setup
tools_setup: command not found
u155004@s005-n003:~$ ls
tmp
u155004@s005-n003:~$ to…
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Hello,
I have a problem to generate the preloader with the DE0_Nano_Soc.
The configuration is the following:
Quartus Lite 18.01 and DS5 standard edition V18.01 on Windows 10,
I followed the proce…
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I have VUnit installed in WSL2 and Modelsim intel edition in windows 10.
I set VUNIT_SIMULATOR and VUNIT_MODELSIM_PATH in **etc/enviroment** and **etc/profile** and **~/.bashrc** to:
`VUNIT_SIMUL…
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# source tcl_files/run.tcl
# vsim -quiet tb -L pulpino_lib -L axi_node_lib -L apb_node_lib -L axi_mem_if_DP_lib -L axi_spi_slave_lib -L axi_spi_master_lib -L apb_uart_sv_lib -L apb_gpio_lib -L apb_ev…
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make
../common/src/AOCLUtils/opencl.cpp: In function ‘_cl_program* aocl_utils::createProgramFromBinary(cl_context, const char*, _cl_device_id* const*, unsigned int)’:
../common/src/AOCLUtils/opencl…
GUUTA updated
3 years ago
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Hi,
I am trying to use OpenCL SDK 17.1 (Quartus Standard ) with De1SoC
I am having a couple of problems
OS Ubuntu
Intel SDK installation
Quartus Prime Lite 17.1
Intel FPGA SDK for OpenCL 1…
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When I run Quick demo with opae driver, there are meaningless performance prints. it seems to take place only in opae driver.
`test-pc@testpc-desktop:~/vortex/build$ ./ci/blackbox.sh --driver=opae …