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I'm going to work on running VTR from edalize, and will track progress here.
- [x] Arch, channel width (#271)
- [ ] Design: including multiple files
- [ ] Flow: Odin or Odin plus Yosys, bitstrea…
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> **Describe the bug**
It looks like if I set up a task with the following in the config/task.conf:
```
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
vpr_fpga_verilog_formal_verifica…
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I use ql_memory_bank shift_register configuration protocol with SRAM cells. SRAM cells have BL, WL and WLR pins as described in ![OpenFPGA Circuit model examples](https://openfpga.readthedocs.io/en/ma…
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# Create a Python library for generating [VtR arch.xml files](https://vtr-verilog-to-routing.readthedocs.io/en/latest/arch/reference.html)
# Brief explanation
Verilog to Routing uses XML files t…
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### Version (or build number)
1.0.0
### Steps to reproduce
-Use RetroDriven/Pocket_Updater v1.5.6 to install this core on a formatted memory card
-Run this core from the FPGA menu, as normal, and …
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**Is your feature request related to a problem? Please describe.**
Currently OpenFPGA generated Verilog netlist used big-endian convention, which is not most conventional way.
Extra care needs to b…
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I left the same comment on the main AP GitHub, but the same thing happens on Worms Armageddon if I load the rom on this openFPGA core rather than use the cartridge. The water does not load, and scroll…
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Screen shifts and wraps around the other side.
to recreate bug the game can be found here: [https://community.arduboy.com/t/the-curse-of-astarok-v1-0-with-sound/8203](url)
walk to the right to ente…
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I’m having issues with the pc engine core where games are very slow to load, the cd audio is defective (sound fx are fine) and the menus are very slow and get stuck. I’m using a 1tb card with all the …
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I want to know if there's way I can do exactly what SOFA is doing but not use skywater standard cells. Is there a way I can just select which standard cell library to use?