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I tried to use AXI_Stream_FIFO v4.2 IP core in Petalinux. I enabled the Xilinx AXI-Stream FIFO v4.1/v4.2 IP core driver directly in the petalinux kernel configuration, but after booting I did not find…
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- [x] Disclose initial draft of the methodology and discuss with WG
- [x] Hardware acceleration across silicon architectures (comparing results across _somewhat_ equivalent commercial solutions) http…
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Hi @maltanar and all, I encounter some errors about synth_1 problems. And u may see below information and report_ip_status, it seems some ip cannot be found. But I follow your steps to generate finn i…
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We need to model AIB channel delay to introduce delay in DV to test CA deskew capability
' wit…
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Hi,
Thank you for sharing this code, it's very informative and useful. I was wondering if you guys had the requirement to do narrow AXI write, if so, what's your solution to do this efficiently?
…
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0.8 DV script runs fixed configuration does not include randomization can you include this please. If you have this script running on Phy2Phy we can use this.
One-text file will address AIB integra…
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Hello,
I met some issues when modifying the Basic mm2s kernel(using the original hls kernel the communication works well). Could you please help me if possible? Thank you!
I am trying to use 's…
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[bug_report_example.zip](https://github.com/EttusResearch/uhd/files/6935936/bug_report_example.zip)
## Issue Description ##
Tx Radio randomly deasserts AXI Stream ready signal after some amount of t…