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It should be very simple to add support for POCL. Our kernels are already SPIR-df when we feed our FPGA target through. We just have some slight strangeness that we need to deal with for our HLS backe…
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I work with a xilinx FPGA (spartan 6), with the ise toolchain, when i try to run the lab002 from fpga_101 i have an xst problem: ERROR: Xst: 2927 - "/home/hyde/Digital/Soc/fpga_101/lab002/build/top.pr…
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I am trying to build FemtoRV petitbateu but it fails to build two different ways for two different toolchains.
When I build with yosys+nextpnr using command: `python3 -m litex_boards.targets.digile…
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I have 2 xilinx targets with MPSOC. multicore arm along side fpga. The 10G ethernet links the targets. This 10G ethernet is xilinx softcore on the fpga portion of SOC(system on chip). I have linux ru…
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Hi,
I was wondering if there are any plans for other FPGA ports. I'd mostly be interested in Zedboard and ZCU102.
In the past these ports (and softcores as standalone projects in general) have bee…
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Hi there
at the very beginning, by using the command I can got the card info, as following.
Card [0000:01:00.0]
Card type: u55n
Flash type: SPI
Flashable partition running on FP…
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Hi,
I am trying to get the pulpino implemented on a Zybo, I followed all the steps in the FPGA directory. everything seems to work correctly when I enter the command "make all", even the synthesis is…
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The various Xilinx CPLD / FPGA libraries have many hundreds of KLC violations and require attention. Some symbols are obsolete and can probably be removed.
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Hello,
Chipyard support rocket with NVDLA, but this project only support VCU118. I want to implement this rocket with NVDLA project on other FPGA prototyping paltform. Which means I can't use Xilinx …
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Hello, I was interested in this project but I see a PCN has been sent this past month announcing EOL for most (it may be all AMD/Xilinx) CPLDs. Last time buy is end of June at least.
Any plans on u…