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I tried Questasim 2021.2, VCS 2018 and the latest version of Verilator. Have you encountered the same problem?
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https://github.com/openhwgroup/cv-hpdcache/blob/645e4222c3d23fbedb5b0fec1922f72fd692a40a/rtl/src/hpdcache_pkg.sv#L76C1-L82C89
The type of the `HPDCACHE_VICTIM_SEL` parameter defined in line 82 of r…
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The most popular open source VHDL verification projects are cocotb, OSVVM and UVVM, along with VUnit. As discussed in [larsasplund.github.io/github-facts](https://larsasplund.github.io/github-facts/),…
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@LarsAsplund, @kraiger and @umarcor,
I would like to propose a broad strategy for co-simulation with VUnit. I really like what @umarcor has been working on, but I think his approach leaves most o…
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There seems to be an error. The shamt on the sbox does not convert correctly when its look at the state from a byte. The original code is on L42 of zknde32.sv
assign shamt = {bs, 3'b0};
The fo…
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Respected Sir
I am trying to install the ARA toolchain in [https://github.com/pulp-platform/ara](ARA) , and while installing it there lies a section where Verilator is required .
i tried running…
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As I follow the build instructions, `configure` does not seem to create `config.h` (even though it says it does).
```
$ ../configure --prefix=$RISCV
checking build system type... x86_64-pc-linux-…
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![image](https://github.com/raysalemi/Python4RTLVerification/assets/98984645/dc903768-9604-46d4-987a-523bc3ce3c0f)
I am trying to run example 23_Basic_testbench_1.0 using the VHDL code.
In the Mak…
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I have slow simulation performance, or if it expected?
Simulation software - QuestaSim 10.7c Linux
CRC Parameters - ByteEnabled version, bus width 512b, pipeline 1.
CPU is rather good Intel i7-9700…
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Hello,
I have an error while trying to build the RTL simulation platform.
I have followed the readme and installed all the requirements.
I work on "Rocky Linux "8.4 (Green Obsidian).
Here is my…
Merok updated
4 months ago