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We have started to do some work but we didn't have an issue for it so I'm creating one.
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The following code does not compile in iverilog. I believe this is valid systemVerilog code. At least one commercial tool accepts this happily. iverilog seems to be unhappy about the datatype and w…
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It appears running Xcelium on the SHA256 (on CPU 1) and IIR (on CPU 2) for the bareMetal test macroMix are failing (timing out) on CEP v4.5. Is this expected and is it fixed or still an issue on CEP …
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I believe in line: https://github.com/IObundle/iob-soc/blob/15268f88d9aae7dfc3df2ecdc736a7d23a8aaa6e/submodules/LIB/hardware/simulation/questa.mk#L12
The "define" should be added to compile flags a…
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After bringing up ASE simulation on ofs-afu/samples and running the host code is giving me these issues.
I'm using an Ubuntu machine with Questasim as simulator.
Error: init.c:205:opae_init() …
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Is the Cosim verification heavily dependent on the randomization and the seed?
I get failures sometimes and I have to change the seed for some tests to pass.
## My Environment
**EDA too…
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I have problem when make all. The project reports an error that many .c and .h files are missing. Can you commit all file to repo ?
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Hi,
I am trying to port synchronous python code to asynchronous with the minimum amount of effort. This code contains about thousand functions with thousand calls which make it annoying to properly…
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Getting assertion error during simulation of the latest version of cva6 on the master using Questasim
The failing assertion in core/pmp/src/pmp.sv :
![image](https://github.com/openhwgroup/cva6/ass…
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Here explain how to run regression inside the axi4_avip project and see how to check the coverage report.