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## Steps to reproduce the issue
I have created an small project to reproduce:
https://github.com/messaging-cells/bug_synth_03
All info to reproduce the bug in the README file.
File with the …
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#### Context
PR #1131 (for issue #1130) is trying to perform a regular sanitizer run of the vtr_reg_basic and vtr_reg_strong regression tests to detect undefined behaviour and memory errors.
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### Environment (OS, Python version, PySpice version, simulator)
OS: Arch Linux
Pyspice version:
```
$ pip show pyspice
Name: PySpice
Version: 1.2.0
Summary: Simulate electronic circuit using …
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When migrating from arachne-pnr to nextpnr, loading a netlist that was converted to JSON, a segfault is triggered at line 624 of `jsonparse.cc` :
```C++
if (GetSize(pdir_node->data_dict_keys) != G…
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Few of Make file test included with verilog-perl (**Verilog-Perl-3.470**) fails. It seems like most of these failures are related to parser errors. Below is a snippet of failing report.
**Commands …
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Hi,
I have this circuit (here it's very simplified, but illustrates the problem I face):
```
I_M 0 N1 0.025
X_entry1 N1 0 N2 entry_1
X_entry2 N1 0 N3 entry_2
.subckt entry_1 m_in m_out v_v…
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It might be of interest to you that the SymbiFlow project has started working on an open source System Verilog compliance suite which can be found at https://github.com/SymbiFlow/sv-tests
It's stil…
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I will publish PR later today.
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**Is your feature request related to a problem? Please describe.**
With the availability of modules, the vhdl parser should be able to parse a netlist with hierarchy.
**The solution we will implem…