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Running 'make TEST="pcap 3" single_hdl_test' on the commit [2dc5f16](https://github.com/PandABlocks/PandABlocks-FPGA/commit/2dc5f16806772fe4a224a0feacde9fa38adbee66), the test result shows:
> The tes…
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Hi Anderson,
I was exploring the RaveNoC Router for the implementation in FPGA domain, as I thought that RaveNoC router is more suited for ASIC design purpose. I have attempted to optimize LUT coun…
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Hi, your README might be a little confusing, so may I ask you three questions?
First of all, your program is written in Haskell, right? So what platform do we need to use to reproduce your program? w…
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Hello, I've been trying to run the HGDB vs code debugger and I'm unsure on how to proceed.
My process thus far:
Obtained the symbol table from hgdb-vitis.
Compiled the circuit with iverilog and…
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## Problem
**Problem: I am running into an issue when attempting to simulate a design using the XPM CDC library in Xilinx Vivado 2022.1 on Ubuntu 20.04.1**
It appears that the CDC library is attem…
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I've written a simple model of an encrypted Xilinx primitive to allow me to simulate my design in GHDL, and a configuration statement to substitute this in when required. I've debugged the model using…
amb5l updated
2 years ago
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Example code:
```verilog
module mod0 (input [3:0] x);
initial begin
$display("%b", x);
$finish;
end
endmodule
module test;
mod0 m ('1);
endmodule
```
Output…
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I've written a simple model of an encrypted Xilinx primitive to allow me to simulate my design in open source simulators, and a configuration statement to substitute this in when required. I've debugg…
amb5l updated
2 years ago
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We currently store the clock period in picoseconds. The limitations of `ps` hasn't been a problem so far, but with the introduction of [dynamic clocks](https://github.com/clash-lang/clash-compiler/pul…
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I'm trying to simulate Verilog modules that are generated automatically using Vivado HLS. Some of these modules refer to auxiliary input files that initialize arrays (using `$readmemh`). Usually, Viva…