-
When interfacing with linters and other tools like LSP's, it would be useful to have some public API to fetch all VUnit source files that should be compiled into `vunit_lib`, including adding `OSVVM` …
-
Hello!
May I ask if this project has any kind of license? I am failing to find any clear information about reusing and distributing this code?
We have used below listed code files as a part for o…
-
**Problem**
When schematic viewer calls `runYosysGhdl()`, it doesn't call `remove_file()` on the `.teroshdl_${random_id}` file that it generates with `createTempFileInHome()`. This results in tempora…
-
Using GHDL as a frontend for Yosys allows synthesising VHDL, Verilog and/or mixed language designs. See https://im-tomu.github.io/fomu-workshop/mixed-hdl.html. It'd be interesting to test whether this…
-
Coming from VUnit/vunit#569...
> [1138-4EB]
> IRRC, subdirs named v93 and v08 are generated by GHDL automatically and you cannot modify their names, you can only set the parent ***@***.***, please…
-
It turns out that Vivado's block design facility has the annoyingly arbitrary limitation that ports may only be of type `std_logic` or `std_logic_vector`. Unfortunately, this means that VHDL produced …
-
I'm experimenting with generic `memory_pkg. vhd` and it seems compile order is not resolved properly:
```
Compiling into vunit_lib: ../logging/src/logger_pkg.vhd passed
Com…
-
This issue was created in repo VHDL/sphinx-vhdl, which was a placeholder (now removed).
> @Nic30
> Hello,
>
> there is some sphinx plugin, which can generate schematic, from HDL.
> [d3-hwschem…
-
can you make the VHDL code so it can be connected dan turn on the LEDs with switches
-
I'd like to experiment using Microwatt as a 64-bit microcontroller on an ECP5 LFE5U-25F. Unfortunately, even with the following patch, I can't seem to get Microwatt _and_ SoC peripherals to fit:
``…