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It appears that the order of the verilog files effects the connectivity.
If the parent verilog is read before the child verilog, a placeholder is created. When the actual verilog is input, the port…
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### Description
Hi,
My setup:
I had a design with a high fanout part, where i had to read a few register based memory array (~2530 muxes to drive from one address).
Symptoms :
In such case…
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I saw you merged a pull request ( https://github.com/bespoke-silicon-group/bsg_fakeram/pull/9 ) which mentions SKY130 but you don't seem to have any example configurations?
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"ext2spice hierarchy off" should flatten a subcircuit until all that is left in the subcircuit are primitive devices.
However, when using the sky130 PDK, it was found that a subcircuit calling the …
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Hello,
I'm trying to generate a padring using the sky130_ef_io cells.
The config file and the LEF are here: [https://github.com/EpSilicon/OpenSource_IC_Design/tree/aaac67b832ec428b2b9f9427061800a5e8…
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Add examples and tests for schematic driven layout to support going from schematic to layout using different schematic capture tools
- [ ] from Ansys Lumerical Interconnect @kithminrw
- [ ] from Xsch…
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Hi @StefanSchippers ,
Regarding the use of `sky13_fd_sc_hd` standard cell library components in xschem and running ngspice, how do we setup ngspice to find the corresponding subckt definitions?
…
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In OpenRAM when creating an SRAM with the following configuration
```word_size = 16
num_words = 256
words_per_row = 1
tech_name = "sky130"
num_banks = 2
num_rw_ports = 1
num_r_ports = 0
nu…
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`Netgen 1.5.253`
Using verilog generated from Cadence Innovus.
1. From sky130 mpw-4 slot-005, the `user_proj_example` has many ports shorted.
```
assign VWPR = VPWR;
assign wbs_ack_o …
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- As we consider SRAM22 for an asic design: Was SRAM22 already taped-out in SKY130 before?
- Would it be possible for external users, who have access to corresponding licenses (or open source tools…
c-93 updated
2 months ago