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When I flash the nist_clock gateware to the kc705, I get a memory initialization failure. This does not happen when I flash the nist_qc1 gateware. Here are the details:
I built the clock gateware usi…
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Hello,
I made an observation on the time yosys invests on my code. This is not about the time the FPGA needs to execute it.
The implementation of for loops is apparently not in a way that the typica…
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To reproduce on `SMP Debian 3.8.13-12~1wheezy~1da x86_64 GNU/Linux`:
```
slave@debian-slave:~/hostmot2-firmware$ . /opt/Xilinx/13.3/ISE_DS/settings64.sh
. /opt/Xilinx/13.3/ISE_DS/EDK/.settings64.sh …
sirop updated
8 years ago
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I am very new to the FPGA world so I might have done something stupid :)
My source file is:
``` python
from myhdl import always, always_comb, always_seq, Signal, ResetSignal, toVerilog, toVHDL, dela…
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Fail the build, or issue a warning. (Sometimes failed-timing bitstreams are still usable)
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I'm trying to run this command,
`python3.5 -m artiq.gateware.targets.kc705 -H qc1 # or qc2`
but get the following error,
```
Traceback (most recent call last):
File "/home/rabi/anaconda3/lib/pyt…
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So I followed your advice https://github.com/LinuxCNC/hostmot2-firmware/issues/1#issuecomment-208885014 and just `make` without dotting Xilinx 13.3 settings before.
All went well until I got to:
``…
sirop updated
8 years ago
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Sorry to file another "issue" :)
We would like to compiling the vendor libraries e.g. from Xilinx ISE for VHDL-93 and VHDL-2008 into the same folder. Currently that's no problem for the `mcode` backe…
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Hello,
I was able to successfully build the blinkie project for the Spartan6 FPGA with Xilinx ISE14.7 (64-Bit) under CentOS6.5.
However, if I try to only synthesize the referenced lm32 core (lm32_to…
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Moving suoto/vim-hdl#4 to hdlcc.
Built-in libraries are statically defined, which means that things will break on different environments. We can either use the compiler to get them somehow or create …
suoto updated
8 years ago